C8051F321R Silicon Laboratories Inc, C8051F321R Datasheet - Page 40

• Manufacturer Part Number: C8051F321R
• Description: IC 8051 MCU 16K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F321R

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: 336-1067-2

C8051F320/1
5.1.
AMUX0 selects the positive and negative inputs to the ADC. Any of the following may be selected as the positive
input: P1.0-P3.0, the on-chip temperature sensor, or the positive power supply (VDD). Any of the following may be
selected as the negative input: P1.0-P3.0, VREF, or GND. When GND is selected as the negative input, ADC0
operates in Single-ended Mode; all other times, ADC0 operates in Differential Mode. The ADC0 input channels
are selected in the AMX0P and AMX0N registers as described in Figure 5.5 and Figure 5.6.
The conversion code format differs between Single-ended and Differential modes. The registers ADC0H and ADC0L
contain the high and low bytes of the output conversion code from the ADC at the completion of each conversion.
Data can be right-justified or left-justified, depending on the setting of the AD0LJST bit (ADC0CN.0). When in Sin-
gle-ended Mode, conversion codes are represented as 10-bit unsigned integers. Inputs are measured from ‘0’ to
VREF * 1023/1024. Example codes are shown below for both right-justified and left-justified data. Unused bits in the
ADC0H and ADC0L registers are set to ‘0’.
When in Differential Mode, conversion codes are represented as 10-bit signed 2’s complement numbers. Inputs are
measured from -VREF to VREF * 511/512. Example codes are shown below for both right-justified and left-justified
data. For right-justified data, the unused MSBs of ADC0H are a sign-extension of the data word. For left-justified
data, the unused LSBs in the ADC0L register are set to ‘0’.
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be configured as
analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for analog input, set to ‘0’ the
corresponding bit in register PnMDIN (for n = 0,1,2,3). To force the Crossbar to skip a Port pin, set to ‘1’ the corre-
sponding bit in register PnSKIP (for n = 0,1,2). See
configuration details.
40
VREF * 1023/1024
VREF * 512/1024
VREF * 256/1024
-VREF * 256/512
VREF * 511/512
VREF * 256/512
(Single-Ended)
Input Voltage
Input Voltage
(Differential)
- VREF
Analog Multiplexer
0
0
Right-Justified ADC0H:ADC0L
Right-Justified ADC0H:ADC0L
(AD0LJST = 0)
(AD0LJST = 0)
0xFE00
0x01FF
0xFF00
0x03FF
0x0100
0x0000
0x0200
0x0100
0x0000
Section “14. Port Input/Output” on page 127
Rev. 1.1
Left-Justified ADC0H:ADC0L
Left-Justified ADC0H:ADC0L
(AD0LJST = 1)
(AD0LJST = 1)
0xFFC0
0x7FC0
0x8000
0x4000
0x0000
0xC000
0x4000
0x0000
0x8000
for more Port I/O