C8051F321 Silicon Laboratories Inc, C8051F321 Datasheet - Page 100

• Manufacturer Part Number: C8051F321
• Description: IC 8051 MCU 16K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F321

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

C8051F320/1
10.1. Power-On Reset
During power-up, the device is held in a reset state and the /RST pin is driven low until VDD settles above V
Power-On Reset delay (T
0.3 ms. Figure 10.2. plots the power-on and VDD monitor reset timing.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is set, all of
the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other resets). Since all resets
cause program execution to begin at the same location (0x0000) software can read the PORSF flag to determine if a
power-up was the cause of reset. The content of internal data memory should be assumed to be undefined after a
power-on reset. The VDD monitor is enabled following a power-on reset.
Software can force a power-on reset by writing ‘1’ to the PINRSF bit in register RSTSRC.
100
Logic HIGH
Logic LOW
Figure 10.2. Power-On and VDD Monitor Reset Timing
2.70
2.4
2.0
1.0
PORDelay
/RST
) occurs before the device is released from reset; this delay is typically less than
V
RST
Power-On
Reset
T
PORDelay
Rev. 1.1
Monitor
Reset
VDD
VDD
t
RST
. A