C8051F321 Silicon Laboratories Inc, C8051F321 Datasheet - Page 233

• Manufacturer Part Number: C8051F321
• Description: IC 8051 MCU 16K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F321

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
TF3H
R/W
Bit7
TF3H: Timer 3 High Byte Overflow Flag.
Set by hardware when the Timer 3 high byte overflows from 0xFF to 0x00. In 16 bit mode, this will
occur when Timer 3 overflows from 0xFFFF to 0x0000. When the Timer 3 interrupt is enabled, set-
ting this bit causes the CPU to vector to the Timer 3 interrupt service routine. TF3H is not automati-
cally cleared by hardware and must be cleared by software.
TF3L: Timer 3 Low Byte Overflow Flag.
Set by hardware when the Timer 3 low byte overflows from 0xFF to 0x00. When this bit is set, an
interrupt will be generated if TF3LEN is set and Timer 3 interrupts are enabled. TF3L will set when
the low byte overflows regardless of the Timer 3 mode. This bit is not automatically cleared by hard-
ware.
TF3LEN: Timer 3 Low Byte Interrupt Enable.
This bit enables/disables Timer 3 Low Byte interrupts. If TF3LEN is set and Timer 3 interrupts are
enabled, an interrupt will be generated when the low byte of Timer 3 overflows. This bit should be
cleared when operating Timer 3 in 16-bit mode.
0: Timer 3 Low Byte interrupts disabled.
1: Timer 3 Low Byte interrupts enabled.
T3SOF: Timer 3 Start-Of-Frame Capture Enable
0: SOF Capture disabled.
1: SOF Capture enabled. Each time a USB SOF is received, the contents of the Timer 3 registers
(TMR3H and TMR3L) are latched into the Timer3 reload registers (TMR3RLH and TMR3RLH),
and a Timer 3 interrupt is generated (if enabled).
T3SPLIT: Timer 3 Split Mode Enable.
When this bit is set, Timer 3 operates as two 8-bit timers with auto-reload.
0: Timer 3 operates in 16-bit auto-reload mode.
1: Timer 3 operates as two 8-bit auto-reload timers.
TR3: Timer 3 Run Control.
This bit enables/disables Timer 3. In 8-bit mode, this bit enables/disables TMR3H only; TMR3L is
always enabled in this mode.
0: Timer 3 disabled.
1: Timer 3 enabled.
UNUSED. Read = 0b. Write = don’t care.
T3XCLK: Timer 3 External Clock Select.
This bit selects the external clock source for Timer 3. If Timer 3 is in 8-bit mode, this bit selects the
external oscillator clock source for both timer bytes. However, the Timer 3 Clock Select bits (T3MH
and T3ML in register CKCON) may still be used to select between the external clock and the system
clock for either timer.
0: Timer 3 external clock selection is the system clock divided by 12.
1: Timer 3 external clock selection is the external clock divided by 8. Note that the external oscillator
source divided by 8 is synchronized with the system clock.
TF3L
R/W
Bit6
Figure 19.24. TMR3CN: Timer 3 Control Register
TF3LEN
R/W
Bit5
T3SOF
R/W
Bit4
T3SPLIT
R/W
Bit3
Rev. 1.1
TR3
R/W
Bit2
R/W
Bit1
-
C8051F320/1
T3XCLK
R/W
Bit0
SFR Address:
00000000
Reset Value
0x91
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