C8051F321 Silicon Laboratories Inc, C8051F321 Datasheet - Page 145
![IC 8051 MCU 16K FLASH 28MLP](/photos/6/93/69391/sl-28-mlp_sml.jpg)
C8051F321
Manufacturer Part Number
C8051F321
Description
IC 8051 MCU 16K FLASH 28MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F32xr
Datasheet
1.C8051F320R.pdf
(256 pages)
Specifications of C8051F321
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Bit7:
Bit6:
Bit5:
Bits4-3:
Bit2:
Bit1:
Bit0:
PREN
R/W
Bit7
PREN: Internal Pull-up Resistor Enable
The location of the pull-up resistor (D+ or D-) is determined by the SPEED bit.
0: Internal pull-up resistor disabled (device effectively detached from the USB network).
1: Internal pull-up resistor enabled when VBUS is present (device attached to the USB network).
PHYEN: Physical Layer Enable
This bit enables/disables the USB0 physical layer transceiver.
0: Transceiver disabled (suspend).
1: Transceiver enabled (normal).
SPEED: USB0 Speed Select
This bit selects the USB0 speed.
0: USB0 operates as a Low Speed device. If enabled, the internal pull-up resistor appears on the D-
line.
1: USB0 operates as a Full Speed device. If enabled, the internal pull-up resistor appears on the D+
line.
PHYTST1-0: Physical Layer Test
These bits can be used to test the USB0 transceiver.
DFREC: Differential Receiver
The state of this bit indicates the current differential value present on the D+ and D- lines when
PHYEN = ‘1’.
0: Differential ‘0’ signaling on the bus.
1: Differential ‘1’ signaling on the bus.
Dp: D+ Signal Status
This bit indicates the current logic level of the D+ pin.
0: D+ signal currently at logic 0.
1: D+ signal currently at logic 1.
Dn: D- Signal Status
This bit indicates the current logic level of the D- pin.
0: D- signal currently at logic 0.
1: D- signal currently at logic 1.
PHYTST[1:0]
PHYEN
R/W
Bit6
00b
01b
10b
11b
Figure 15.2. USB0XCN: USB0 Transceiver Control
SPEED
R/W
Bit5
Mode
Mode 0: Normal (non-test mode)
Mode 1: Differential ‘1’ Forced
Mode 2: Differential ‘0’ Forced
Mode 3: Single-Ended ‘0’ Forced
PHYTST1 PHYTST0
R/W
Bit4
R/W
Bit3
Rev. 1.1
DFREC
Bit2
R
D+
X
1
0
0
D-
X
0
1
0
Bit1
Dp
R
C8051F320/1
Bit0
Dn
R
SFR Address:
00000000
Reset Value
0xD7
145
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