R8A77850ADBGV Renesas Electronics America, R8A77850ADBGV Datasheet - Page 1125

• Manufacturer Part Number: R8A77850ADBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

(6)
Figure 21.21 shows a sample flowchart for transmitting and receiving data simultaneously.
Use the following procedure for the simultaneous serial transmission/reception of serial data, after
enabling the SCIF transmission/reception.
No
No
No
Transmitting and Receiving Serial Data Simultaneously (Clocked Synchronous Mode)
Write transmit data to SCFTDR, and
clear TDFE flag in SCFSR to 0
Read receive data in SCFRDR, and
clear RDF flag in SCFSR to 0
Clear TE and RE bits in SCSCR to 0
Start of transmission and reception
End of transmission and reception
Figure 21.21 Sample Flowchart for Transmitting/Receiving Serial Data
Read ORER flag in SCLSR
Read TDFE flag in SCFSR
Read RDF flag in SCFSR
All data received?
ORER = 1 ?
Initialization
TDFE = 1 ?
RDF = 1 ?
Yes
No
Yes
Yes
Error handling
[1]
[2]
[4]
[5]
Yes
[3]
21. Serial Communication Interface with FIFO (SCIF)
[1]
[2]
[3]
[4]
[5]
Note: When switching from a transmit operation or receive
To continue serial transmission and reception, read
SCIF initialization:
See Sample SCIF Initialization Flowchart in figure
21.16.
SCIF status check and transmit data write:
Read SCFSR and check that the TDFE flag is set to 1,
then write transmit data to SCFTDR, and clear the
TDFE flag to 0. The transition of the TDFE flag from 0
to 1 can also be identified by a TXI interrupt.
Receive error handling:
Read the ORER flag in SCLSR to identify any error,
perform the appropriate error handling, then clear the
ORER flag to 0. Reception cannot be resumed while
the ORER flag is set to 1.
SCIF status check and receive data read:
Read SCFSR and check that RDF = 1, then read the
receive data in SCFRDR, and clear the RDF flag to 0.
The transition of the RDF flag from 0 to 1 can also be
identified by an RXI interrupt.
Serial transmission and reception continuation
procedure:
RDF flag and SCFRDR, and clear the RDF flag to 0
before receiving the MSB in the current frame.
Similarly, read 1 from the TDFE flag to confirm that
writing is possible before transmitting the MSB in the
current frame. Then write data to SCFTDR and clear
the TDFE flag to 0.
operation to simultaneous transmission and reception
operations, clear the TE and RE bits to 0, and then set
them simultaneously to 1.
Rev.1.00 Jan. 10, 2008 Page 1093 of 1658
REJ09B0261-0100