R8A77850ADBGV Renesas Electronics America, R8A77850ADBGV Datasheet - Page 189

• Manufacturer Part Number: R8A77850ADBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit
31 to 26 LRUI
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Bit Name
R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
31
15
0
0
30
14
0
0
Initial
Value
000000
29
13
0
0
LRUI
URC
28
12
0
0
R/W
R/W
27
11
0
0
26
10
0
0
Description
Least Recently Used ITLB
These bits indicate the ITLB entry to be replaced. The
LRU (least recently used) method is used to decide the
ITLB entry to be replaced in the event of an ITLB miss.
The entry to be purged from the ITLB can be confirmed
using the LRUI bits.
LRUI is updated by means of the algorithm shown below.
x means that updating is not performed.
000xxx: ITLB entry 0 is used
1xx00x: ITLB entry 1 is used
x1x1x0: ITLB entry 2 is used
xx1x11: ITLB entry 3 is used
xxxxxx: Other than above
When the LRUI bit settings are as shown below, the
corresponding ITLB entry is updated by an ITLB miss.
Ensure that values for which "Setting prohibited" is
indicated below are not set at the discretion of software.
After a power-on or manual reset, the LRUI bits are
initialized to 0, and therefore a prohibited setting is never
made by a hardware update.
x means "don't care".
111xxx: ITLB entry 0 is updated
0xx11x: ITLB entry 1 is updated
x0x0x1: ITLB entry 2 is updated
xx0x00: ITLB entry 3 is updated
Other than above: Setting prohibited
SQMD SV
25
R
0
0
9
24
R
0
8
0
R/W R/W R/W R/W R/W R/W
R/W
ME
23
0
0
7
Rev.1.00 Jan. 10, 2008 Page 157 of 1658
22
0
R
0
6
7. Memory Management Unit (MMU)
21
0
R
0
5
URB
20
0
R
0
4
19
0
R
0
3
R/W
REJ09B0261-0100
18
TI
0
2
0
17
R
0
1
0
R
R/W
AT
16
R
0
0
0