R8A77850ADBGV Renesas Electronics America, R8A77850ADBGV Datasheet - Page 1316

• Manufacturer Part Number: R8A77850ADBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

25. Audio Codec Interface (HAC)
25.3.10 HAC Control Register (HACACR)
HACACR is a 32-bit read/write register used for controlling the HAC interface.
Rev.1.00 Jan. 10, 2008 Page 1284 of 1658
REJ09B0261-0100
Initial value:
Initial value:
Bit
31
30
29
28, 27
26
R/W:
R/W:
Bit:
Bit:
Bit Name
⎯
DMARX16
DMATX16
⎯
TX12_ATOMIC
⎯
31
15
⎯
R
R
1
0
RX16
DMA
R/W
⎯
30
14
R
0
0
TX16
DMA
R/W
29
13
⎯
R
0
0
Initial
Value
1
0
0
All 0
1
28
12
⎯
⎯
R
R
0
0
R/W
R
R/W
R/W
R
R/W
⎯
27
⎯
11
R
R
0
0
ATOMIC
TX12_
R/W
⎯
26
10
R
1
0
Description
Reserved
This bit is always read as 1. The write value should
always be 1.
16-bit RX DMA Enable
0: Disables 16-bit packed RX DMA mode. Enables the
1: Enables 16-bit packed RX DMA mode. Disables the
16-bit TX DMA Enable
0: Disables 16-bit packed TX DMA mode. Enables the
1: Enables 16-bit packed TX DMA mode. Disables the
Reserved
These bits are always read as 0. The write value should
always be 0.
TX Slot 1 and 2 Atomic Control
0: Transmits TX data in HACCSAR and that in
1: Transmits TX data in HACCSAR and that in
⎯
25
⎯
RXDMAL_EN and RXDMAR_EN settings.
RXDMAL_EN and RXDMAR_EN settings.
TXDMAL_EN and TXDMAR_EN settings.
TXDMAL_EN and TXDMAR_EN settings.
HACCSDR separately. (Setting prohibited)
HACCSDR in the same frame if bit 19 in HACCSAR
is 0 (write). (HACCSAR must be written last.)
R
R
0
9
0
RXDMAL
R/W
24
_EN
⎯
R
0
8
0
TXDMAL
R/W
_EN
23
⎯
R
0
7
0
RXDMAR
R/W
_EN
22
⎯
R
6
0
0
TXDMAR
R/W
_EN
21
⎯
R
0
5
0
20
⎯
⎯
R
R
0
4
0
19
⎯
⎯
R
R
0
3
0
18
⎯
⎯
R
R
0
2
0
⎯
17
⎯
R
R
0
1
0
16
⎯
R
R
⎯
0
0
0