R8A77850ADBGV Renesas Electronics America, R8A77850ADBGV Datasheet - Page 1151

• Manufacturer Part Number: R8A77850ADBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit
10
9
8
7, 6
5
4
3
2
1
0
Bit Name
RCRDYE
RFFULE
RDREQE
⎯
SAERRE
FSERRE
TFOVFE
TFUDFE
RFUDFE
RFOVFE
Initial
Value
0
0
0
All 0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Description
Receive Control Data Ready Enable
0: Disables interrupts due to receive control data ready
1: Enables interrupts due to receive control data ready
Receive FIFO Full Enable
0: Disables interrupts due to receive FIFO full
1: Enables interrupts due to receive FIFO full
Receive Data Transfer Request Enable
0: Disables interrupts due to receive data transfer
1: Enables interrupts due to receive data transfer
Reserved
These bits are always read as 0. The write value should
always be 0.
Slot Assign Error Enable
0: Disables interrupts due to slot assign error
1: Enables interrupts due to slot assign error
Frame Synchronization Error Enable
0: Disables interrupts due to frame synchronization
1: Enables interrupts due to frame synchronization error
Transmit FIFO Overflow Enable
0: Disables interrupts due to transmit FIFO overflow
1: Enables interrupts due to transmit FIFO overflow
Transmit FIFO Underflow Enable
0: Disables interrupts due to transmit FIFO underflow
1: Enables interrupts due to transmit FIFO underflow
Receive FIFO Underflow Enable
0: Disables interrupts due to receive FIFO underflow
1: Enables interrupts due to receive FIFO underflow
Receive FIFO Overflow Enable
0: Disables interrupts due to receive FIFO overflow
1: Enables interrupts due to receive FIFO overflow
requests
requests
error
Rev.1.00 Jan. 10, 2008 Page 1119 of 1658
22. Serial I/O with FIFO (SIOF)
REJ09B0261-0100