R8A77850ADBGV Renesas Electronics America, R8A77850ADBGV Datasheet - Page 536

• Manufacturer Part Number: R8A77850ADBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

12. DDR2-SDRAM Interface (DBSC2)
12.4.11 SDRAM Refresh Status Register (DBRFSTS)
The SDRAM refresh status register (DBRFSTS) is a readable/writable register. It is initialized
only upon power-on reset.
Rev.1.00 Jan. 10, 2008 Page 504 of 1658
REJ09B0261-0100
Initial value:
Initial value:
Bit
31 to 1
0
R/W:
R/W:
BIt:
BIt:
Bit Name
⎯
RFUDF
31
15
⎯
⎯
R
R
0
0
30
⎯
14
⎯
R
R
0
0
29
⎯
13
⎯
Initial
Value
All 0
0
R
R
0
0
28
12
⎯
⎯
R
R
0
0
27
11
⎯
⎯
R
R
0
0
R/W
R
R/W
26
10
⎯
⎯
R
R
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
Refresh Counter Underflow Bit
Set to 1 to indicate that the refresh counter has
underflows when the refresh counter changes from 1 to
0. This bit is cleared to 0 by writing 0 to it.
Underflow may occur because the LV0TH bit value is
smaller than the maximum number of command
execution cycles, so that refresh cannot be issued until
the counter value reaches 0. In this case, the value of
the LV0TH bit should be changed.
For details on the refresh counter, refer to section
12.5.5, Auto-Refresh Operation.
0: Indicates that no underflow occurs.
1: Indicates that an underflow occurs.
25
⎯
⎯
R
R
0
9
0
24
⎯
⎯
R
R
0
8
0
23
⎯
⎯
R
R
0
7
0
22
⎯
⎯
R
R
0
6
0
21
⎯
⎯
R
R
0
5
0
20
⎯
⎯
R
R
0
4
0
19
⎯
⎯
R
R
0
3
0
18
⎯
⎯
R
R
0
2
0
17
⎯
⎯
R
R
0
1
0
RFUDF
R/W
16
⎯
R
0
0
0