R8A77850ADBGV Renesas Electronics America, R8A77850ADBGV Datasheet - Page 262

• Manufacturer Part Number: R8A77850ADBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ADBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

8. Caches
• FLUSH transaction
(3)
Of the operand cache operating instructions, the coherency control-related specifications of OCBI,
OCBP, and OCBWB have been changed from those of the SH-4A with H'20-valued VER bits in
the processor version register (PVR).
• Changes in the invalidate instruction OCBI@Rn
• Changes in the purge instruction OCBP@Rn
• Changes in the write-back instruction OCBWB@Rn
Rev.1.00 Jan. 10, 2008 Page 230 of 1658
REJ09B0261-0100
When the operand cache is enabled, the FLUSH transaction checks the operand cache and if
the hit line is dirty, then the data is written back to the external memory. If the transaction is
not hit to the cache or the hit entry is not dirty, it is no-operation.
When Rn is designating an address in a non-cacheable area, this instruction is executed as
NOP in the SH-4A with H'20-valued VER bits in the processor version register (PVR). In this
LSI, this instruction invalidates the operand cache line designated by way = Rn[14:13] and
entry = Rn[12:5] provided that Rn[31:24] = H'F4 (OC address array area). In this process,
writing back of the line does not take place even if the line to be invalidated is dirty. This
operation is only executable in privileged mode, and an address error exception occurs in user
mode. TLB-related exceptions do not occur.
Do not execute this instruction to invalidate the memory-mapped array areas and control
register areas for which Rn[31:24] is not H'F4, and their reserved areas (H'F0 to H'F3, H'F5 to
H'FF).
When Rn is designating an address in a non-cacheable area, this instruction is executed as
NOP in the SH-4A with H'20-valued VER bits in the processor version register (PVR). In this
LSI, this instruction invalidates the operand cache line designated by way = Rn[14:13] and
entry = Rn[12:5] provided that Rn[31:24] = H'F4 (OC address array area). In this process,
writing back of the line takes place when the line to be invalidated is dirty. This operation is
only executable in privileged mode, and an address error exception occurs in user mode. TLB-
related exceptions do not occur.
Do not execute this instruction to invalidate the memory-mapped array areas and control
register areas for which Rn[31:24] is not H'F4, and their reserved areas (H'F0 to H'F3, H'F5 to
H'FF).
When Rn is designating an address in a non-cacheable area, this instruction is executed as
NOP in the SH-4A with H'20-valued VER bits in the processor version register (PVR). In this
LSI, provided that Rn[31:24] = H'F4 (OC address array area), this instruction writes back the
operand cache line designated by way = Rn[14:13] and entry = Rn[12:5] if it is dirty and clears
Changes in Instruction Specifications Regarding Coherency Control