R8A77850ADBGV Renesas Electronics America, R8A77850ADBGV Datasheet - Page 883
R8A77850ADBGV
Manufacturer Part Number
R8A77850ADBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ADBGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850ADBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
R8A77850ADBGV#RD0Z
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Bit
16
15
14
Bit Name
DFB1
TVR
FRM
0
Initial
Value
0
0
R/W
R
R
R
Internal
Update
None
None
None
Description
Display Frame Buffer 1 Flag
0: The address indicated by the plane 1 display
1: The address indicated by the plane 1 display
TV Synchronization Error Flag
0: After using the DRES bit in DSYSR or the
1: Indicates that the rising edge of EXVSYNC
Frame Flag
0: After clearing to 0 the FRM bit using either the
1: After clearing to 0 the FRM bit using either the
area start address 0 register (P1DSA0R) in
plane 1 is being used as the display area start
address
area start address 0 register (P1DSA1R) in
plane 1 is being used as the display area start
address
TVCL bit in the display status register clear
register (DSRCR) to clear the TVR bit to 0,
indicates that the rising edge of EXVSYNC is
being detected each time within the vertical
period determined by the setting of the
vertical scan period register (VCR).
was not detected within the vertical period
determined by the setting of VCR when in TV
sync mode.
The TVR bit holds its state until cleared to 0
by the DRES bit in DSYSR or by the TVCL bit
in DSRCR.
DRES bit in DSYSR or the FRCL bit in
DSRCR, in interlaced mode indicates the
interval to the next display end, and in
interlaced sync mode or in interlaced sync &
video mode indicates the interval to the
display end of the next even field.
DRES bit in DSYSR or the FRCL bit in
DSRCR, indicates the interval until the next
time the FRM bit is cleared, from the first
vertical blanking interval in non-interlaced
mode, and from the first even field blanking
interval in interlaced sync or in interlaced sync
& video mode. (frame units)
Rev.1.00 Jan. 10, 2008 Page 851 of 1658
19. Display Unit (DU)
REJ09B0261-0100
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