AD625JNZ Analog Devices Inc, AD625JNZ Datasheet - Page 11

• Manufacturer Part Number: AD625JNZ
• Description: IC AMP INST 25MHZ LN 16DIP
• Manufacturer: Analog Devices Inc
• Type: Low Noiser

Specifications of AD625JNZ

• Amplifier Type: Instrumentation
• Number Of Circuits: 1
• Slew Rate: 5 V/µs
• Gain Bandwidth Product: 25MHz
• -3db Bandwidth: 650kHz
• Current - Input Bias: 30nA
• Voltage - Input Offset: 50µV
• Current - Supply: 3.5mA
• Voltage - Supply, Single/dual (±): ±6 V ~ 18 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Bandwidth: 650 kHz
• Common Mode Rejection Ratio: 75
• Current, Input Bias: ±30 nA
• Current, Input Offset: ±2 nA
• Current, Output: 5 mA
• Current, Supply: 3.5 mA
• Number Of Amplifiers: Five
• Package Type: PDIP-16
• Power Dissipation: 450 mW
• Resistance, Input: 1 Gigaohms
• Temperature, Operating, Range: 0 to +70 °C
• Voltage, Input Offset: 50 μV
• Voltage, Noise: 4 nV/sqrt Hz
• Voltage, Output Swing: ±10 V
• Voltage, Supply: ±6 to ±18 V
• No. Of Amplifiers: 5
• Input Offset Voltage: 200µV
• Gain Db Min: 1dB
• Amplifier Output: Single Ended
• Cmrr: 115dB
• Supply Voltage Range: ± 6V To ± 18V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output Type: -
• Current - Output / Channel: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Offset voltage and offset voltage drift each have two compo-
nents: input and output. Input offset is that component of offset
that is generated at the input stage. Measured at the output it is
directly proportional to gain, i.e., input offset as measured at the
output at G = 100 is 100 times greater than that measured at
G = 1. Output offset is generated at the output and is constant
for all gains.
The input offset and drift are multiplied by the gain, while the
output terms are independent of gain, therefore, input errors
dominate at high gains and output errors dominate at low gains.
The output offset voltage (and drift) is normally specified at
G = 1 (where input effects are insignificant), while input offset
(and drift) is given at a high gain (where output effects are negli-
gible). All input-related parameters are specified referred to the
input (RTI) which is to say that the effect on the output is “G”
times larger. Offset voltage vs. power supply is also specified as
an RTI error.
By separating these errors, one can evaluate the total error inde-
pendent of the gain. For a given gain, both errors can be com-
bined to give a total error referred to the input (RTI) or output
(RTO) by the following formula:
Total Error RTI = input error + (output error/gain)
Total Error RTO = (Gain × input error) + output error
The AD625 provides for both input and output offset voltage
adjustment. This simplifies nulling in very high precision appli-
cations and minimizes offset voltage effects in switched gain
applications. In such applications the input offset is adjusted
first at the highest programmed gain, then the output offset is
adjusted at G = 1. If only a single null is desired, the input offset
null should be used. The most additional drift when using only
the input offset null is 0.9 µV/°C, RTO.
COMMON-MODE REJECTION
Common-mode rejection is a measure of the change in output
voltage when both inputs are changed by equal amounts. These
specifications are usually given for a full-range input voltage
change and a specified source imbalance.
In an instrumentation amplifier, degradation of common-mode
rejection is caused by a differential phase shift due to differences
SIGNAL
INPUT
+V
S
AD7502
–V
S
+V
AD625
S
–V
S
HOLD
CAP
in distributed stray capacitances. In many applications shielded
cables are used to minimize noise. This technique can create
common-mode rejection errors unless the shield is properly
driven. Figures 32 and 33 show active data guards which are
configured to improve ac common-mode rejection by “boot-
strapping” the capacitances of the input cabling, thus minimiz-
ing differential phase shift.
GROUNDING
In order to isolate low level analog signals from a noisy digital
environment, many data-acquisition components have two or
more ground pins. These grounds must eventually be tied to-
gether at one point. It would be convenient to use a single
ground line, however, current through ground wires and pc runs
of the circuit card can cause hundreds of millivolts of error.
Therefore, separate ground returns should be provided to mini-
mize the current flow from the sensitive points to the system
ground (see Figure 34). Since the AD625 output voltage is
developed with respect to the potential on the reference termi-
nal, it can solve many grounding problems.
SAMPLE
–V
AD583
HOLD
AND
S
+V
S
100
100
ANALOG
STATUS
OUT
+V
–V
+INPUT
–INPUT
AD712
S
S
100
+INPUT
–INPUT
CONVERTER
AD574A
AD711
–V
A/D
S
ANALOG POWER
R
R
R
G
F
F
GROUND
COMMON
DIGITAL
R
R
R
G
F
F
V
AD625
LOGIC
+V
–V
AD625
S
S
–V
+V
S
S
SENSE
REFERENCE
AD625
REFERENCE
SENSE
V
OUT
V
OUT