TLE4271-2S Infineon Technologies, TLE4271-2S Datasheet - Page 3

• Manufacturer Part Number: TLE4271-2S
• Description: IC REGULATOR LDO 5V TO220-7
• Manufacturer: Infineon Technologies

Specifications of TLE4271-2S

• Regulator Topology: Positive Fixed
• Voltage - Output: 5V
• Voltage - Input: 6 ~ 40 V
• Voltage - Dropout (typical): 0.35V @ 550mA
• Number Of Regulators: 1
• Current - Output: 550mA (Max)
• Current - Limit (min): 650mA
• Operating Temperature: -40°C ~ 150°C
• Mounting Type: Through Hole
• Package / Case: TO-220-7 (Straight Leads)
• Number Of Outputs: 1
• Polarity: Positive
• Input Voltage Max: 40 V
• Output Voltage: 5 V
• Output Type: Fixed
• Dropout Voltage (max): 0.7 V at 550 mA
• Output Current: 550 mA
• Load Regulation: 50 mV
• Voltage Regulation Accuracy: 2 %
• Maximum Operating Temperature: + 150 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: SP000013202; SP000306320; TLE42712S

Circuit Description
The control amplifier compares a reference voltage, which is kept highly accurate by
resistance adjustment, to a voltage that is proportional to the output voltage and drives
the base of a series transistor via a buffer. Saturation control as a function of the load
current prevents any over-saturation of the power element.
The reset output RO is in high-state if the voltage on the delay capacitor
equal
greater than the reset threshold
condition’) a fast discharge of the delay capacitor
lower than
The time for the delay capacitor charge from
When the voltage on the delay capacitor has reached
watchdog circuit is enabled and discharges
no rising edge observed at the watchdog input,
reset output RO will be set to low and
V
If the watchdog pulse (rising edge at watchdog input WI) occurs during the discharge
period
the periodical behavior starts again.
Internal protection circuits protect the IC against:
•
•
•
•
Data Sheet
D
reaches
Overload
Overvoltage
Overtemperature
Reverse polarity
V
C
UD
D
. The delay capacitor
is charged again and the reset output stays high. After
V
V
LD
UD
the reset output RO is set to low-level.
and reset will be set high again.
C
V
D
RT
is charged with the current
. If the output voltage gets lower than
C
D
will be charged again with the current
3
C
V
D
UD
with the constant current
C
D
to
will be discharge down to
C
V
D
LD
V
sets in and as soon as
UD
is the reset delay time
and reset was set to high, the
I
D
V
D
for output voltages
Rev. 2.7, 2007-06-25
has reached
C
I
DWD
D
TLE 4271-2
is greater or
V
V
. If there is
RT
I
LDW
t
DWC
V
D
.
(‘reset
D
, then
V
gets
until
UD
,