XC56309VF100A Freescale Semiconductor, XC56309VF100A Datasheet - Page 18

• Manufacturer Part Number: XC56309VF100A
• Description: IC DSP 24BIT FIXED-POINT 196-BGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of XC56309VF100A

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DSP56309 Overview
The PCU uses the following registers:
1.6.4 PLL and Clock Oscillator
The clock generator in the DSP56300 core comprises two main blocks: the PLL, which performs
clock input division, frequency multiplication, and skew elimination; and the clock generator,
which performs low-power division and clock pulse generation. These features allow you to:
The PLL allows the processor to operate at a high internal clock frequency using a low-frequency
clock input, a feature that offers two immediate benefits:
1.6.5 JTAG TAP and OnCE Module
In the DSP56300 core is a dedicated user-accessible TAP that is fully compatible with the IEEE
1149.1 Standard Test Access Port and Boundary Scan Architecture . Problems with testing
high-density circuit boards led to the development of this standard under the sponsorship of the
Test Technology Committee of IEEE and the JTAG. The DSP56300 core implementation
supports circuit-board test strategies based on this standard. The test logic includes a TAP with
four dedicated signals, a 16-state controller, and three test data registers. A boundary scan
1-8
Internal memory-expandable hardware stack
Nested hardware DO loops
Fast auto-return interrupts
Hardware system stack
Program counter register
Status register
Loop address register
Loop counter register
Vector base address register
Size register
Stack pointer
Operating mode register
Stack counter register
Change the low-power divide factor without losing the lock
Output a clock with skew elimination
A lower-frequency clock input reduces the overall electromagnetic interference generated
by a system.
The ability to oscillate at different frequencies reduces costs by eliminating the need to
add additional oscillators to a system.
DSP56309 User’s Manual, Rev. 1
Freescale Semiconductor