XC56309VF100A Freescale Semiconductor, XC56309VF100A Datasheet - Page 22

• Manufacturer Part Number: XC56309VF100A
• Description: IC DSP 24BIT FIXED-POINT 196-BGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of XC56309VF100A

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DSP56309 Overview
1.9 Peripherals
In addition to the core features, the DSP56309 provides the following peripherals:
1.9.1 GPIO Functionality
The GPIO port consists of up to 34 programmable signals, also used by the peripherals (HI08,
ESSI, SCI, and timer). There are no dedicated GPIO signals. After a reset, the signals are
automatically configured as GPIO. Three memory-mapped registers per peripheral control GPIO
functionality. Programming techniques for these registers to control GPIO functionality are
detailed in Chapter 5, Programming the Peripherals.
1.9.2 HI08
The HI08 is a byte-wide, full-duplex, double-buffered parallel port that can connect directly to
the data bus of a host processor. The HI08 supports a variety of buses and provides connection
with a number of industry-standard DSPs, microcomputers, and microprocessors without
requiring any additional logic. The DSP core treats the HI08 as a memory-mapped peripheral
occupying eight 24-bit words in data memory space. The DSP can use the HI08 as a
memory-mapped peripheral, using either standard polled or interrupt programming techniques.
Separate double-buffered transmit and receive data registers allow the DSP and host processor to
transfer data efficiently at high speed. Memory mapping allows you to program DSP core
communication with the HI08 registers using standard instructions and addressing modes.
1.9.3 ESSI
The DSP56309 provides two independent and identical ESSIs. Each ESSI has a full-duplex serial
port for communication with a variety of serial devices, including one or more industry-standard
codecs, other DSPs, microprocessors, and peripherals that implement the Freescale SPI. The
ESSI consists of independent transmitter and receiver sections and a common ESSI clock
generator. ESSI capabilities include the following:
1-12
As many as 34 user-configurable GPIO signals
HI08 to external hosts
Dual ESSI
SCI
Triple timer module
Memory switch mode
Four external interrupt/mode control lines
Independent (asynchronous) or shared (synchronous) transmit and receive sections with
separate or shared internal/external clocks and frame syncs
Normal mode operation using frame sync
DSP56309 User’s Manual, Rev. 1
Freescale Semiconductor