XC56309VF100A Freescale Semiconductor, XC56309VF100A Datasheet - Page 215

• Manufacturer Part Number: XC56309VF100A
• Description: IC DSP 24BIT FIXED-POINT 196-BGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of XC56309VF100A

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

9.4.3 Timer Prescaler Count Register (TPCR)
The TPCR is a read-only register that reflects the current value in the prescaler counter.
Freescale Semiconductor
Bit Number
Bit Number
PC11
23
11
22–21
20–0
23–21
20–0
23
PC10
Reserved bit; read as 0; write to 0 for future compatibility
22
10
Bit Name
PL[20–0]
Table 9-2. Timer Prescaler Count Register (TPCR) Bit Definitions
Bit Name
PC[20–0]
PS[1–0]
Table 9-1. Timer Prescaler Load Register (TPLR) Bit Definitions
PC9
21
9
Figure 9-22. Timer Prescaler Count Register (TPCR)
Reset Value
Reset Value
PC20
PC8
20
8
0
0
0
0
0
PC19
PC7
DSP56309 User’s Manual, Rev. 1
19
7
Reserved. Write to zero for future compatibility.
Prescaler Counter Value
Contain the current value of the prescaler counter.
Reserved. Write to zero for future compatibility.
Prescaler Source
Control the source of the prescaler clock. The prescaler’s use of a TIO signal
is not affected by the TCSR settings of the timer of the corresponding TIO
signal. If the prescaler source clock is external, the prescaler counter is
incremented by signal transitions on the TIO signal. The external clock is
internally synchronized to the internal clock. The external clock frequency
must be lower than the DSP56309 internal operating frequency divided by 4
(that is, CLK/4).
Note:
Prescaler Preload Value
Contains the prescaler preload value, which is loaded into the prescaler
counter when the counter value reaches 0 or the counter switches state from
disabled to enabled. If PL[20–0] = N, then the prescaler counts N+1 source
clock cycles before generating a prescaler clock pulse. Therefore, the
prescaler divide factor = (preload value) + 1.
PS1
PC18
PC6
0
0
1
1
18
6
To ensure proper operation, change the PS[1–0] bits only when the
prescaler counter is disabled. Disable the prescaler counter by
clearing TCSR[TE] of each of three timers.
PC17
PC5
17
5
PS0
0
1
0
1
PC16
PC4
16
4
Description
Description
Triple Timer Module Programming Model
PC15
PC3
15
3
Prescaler Clock Source
PC14
PC2
14
Internal CLK/2
2
TIO0
TIO1
TIO2
PC13
PC1
13
1
PC12
PC0
12
0
9-23