XC56309VF100A Freescale Semiconductor, XC56309VF100A Datasheet - Page 270

• Manufacturer Part Number: XC56309VF100A
• Description: IC DSP 24BIT FIXED-POINT 196-BGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of XC56309VF100A

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Index
Bus Page Logic Enable (BPLE) bit 4-25
Bus Program Memory Enable (BPEN) bit 4-27
Bus Refresh Enable (BREN) bit 4-24
Bus Refresh Prescaler (BRP) bit 4-24
Bus Refresh Rate (BRF) bit 4-24
Bus Release Timing (BRT) bit 4-13
Bus Request Hold (BRH) bit 4-22
Bus Row Out-of-Page Wait States (BRW) bit 4-25
Bus Software Triggered Reset (BSTR) bit 4-24
Bus X Data Memory Enable (BXEN) bit 4-27
Bus Y Data Memory Enable (BYEN) bit 4-27
C
Cache Burst Mode Enable (BE) bit 4-14
Cache Enable (CE) bit 4-7
Carry (C) bit 4-11
Central Processing Unit (CPU) 1-1
Chip Operating Mode (MD–MA) bits 4-14
chip-select
Clock 2-4
Clock Divider (CD) bits 8-17
clock generator 7-10
Clock Generator (CLKGEN) 1-8
Clock Out Divider (COD) 8-17
Clock Output Disable (COD) bit 4-20
Clock Polarity (CKP) bit 7-20
Clock Prescaler (SCP) 8-17
Clock Source Direction (SCKD) bit 7-21
CMOS 1-5
codec 7-3
COM byte 4-12
Command Vector Register (CVR) 6-21
Condition Code Register (CCR) 4-7
Control Register A (CRA)
Index-2
logic 6-16
signal 6-3
Host Command (HC) 6-24
Host Vector (HV) 6-24
programming sheet B-21
Carry (C) 4-11
Extension (E) 4-11
Limit (L) 4-10
Negative (N) 4-11
Overflow (V) 4-11
Scaling (S) 4-10
Unnormalized (U) 4-11
Zero (Z) 4-11
Alignment Control (ALC) 7-14
Frame Rate Divider Control (DC) 7-15
Prescale Modulus Select (PM) 7-15
Prescaler Range (PSR) 7-15
programming sheet B-23
Select SCK (SSC1) 7-13
Word Length Control (WL) 7-14
,
7-9
,
7-11
,
7-16
,
4-8
,
6-24
DSP56309 User’s Manual, Rev. 1
Control Register B (CRB)
Core Priority (CP) bits 4-8
Core-DMA Priority (CDP) bits 4-14
crystal frequency 8-6
Crystal Range (XTLR) bit 4-21
D
data and control host processor registers 6-12
Data Arithmetic Logic Unit (Data ALU) 1-6
Data Input (DI) bit 9-25
data memory expansion 1-9
Data Output (DO) bit 9-25
data strobe 6-3
data transfer methods 5-2
Debug support 1-5
Direct Memory Access (DMA) 6-5
Direction (DIR) bit 9-25
Division Factor (DF) bits 4-21
DMA Address Mode (DAM) bit 4-33
DMA Channel Enable (DE) bit 4-28
DMA Channel Priority (DPR) bit 4-30
DMA Continuous Mode Enable (DCON) bit 4-31
DMA Control Registers (DCR5–DCR0)
DMA Control Registers (DCRs) 4-28
Clock Polarity (CKP) 7-20
Clock Source Direction (SCKD) 7-21
Frame Sync Length (FSL) 7-21
Frame Sync Polarity (FSP) 7-20
Frame Sync Relative Timing (FSR) 7-21
Mode Select (MOD) 7-20
programming sheet B-24
Receive Enable (RE) 7-19
Receive Exception Interrupt Enable (REIE) 7-18
Receive Interrupt Enable (RIE) 7-18
Receive Last Slot Interrupt Enable (RLIE) 7-18
Serial Control Direction 0 (SCD0) 7-22
Serial Control Direction 1 (SCD1) 7-22
Serial Control Direction 2 (SCD2) 7-21
Serial Output Flag 0 (OF0) 7-22
Serial Output Flag 1 (OF1) 7-22
Shift Directions (SHFD) 7-21
Synchronous/Asynchronous (SYN) 7-20
Transmit 0 Enable (TE0) 7-19
Transmit 1 Enable (TE1) 7-19
Transmit 2 Enable (TE2) 7-20
Transmit Exception Interrupt Enable (TEIE) 7-18
Transmit Interrupt Enable (TIE) 7-18
Transmit Last Slot Interrupt Enable (TLIE) 7-18
Request Source bits 4-28
transfers and host bus 6-8
triggered by timer 9-21
programming sheet B-17
bit definitions 4-28
DMA Address Mode (DAM) 4-33
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Freescale Semiconductor
6-8