XR16M2550IL32-F Exar Corporation, XR16M2550IL32-F Datasheet - Page 34
XR16M2550IL32-F
Manufacturer Part Number
XR16M2550IL32-F
Description
IC UART FIFO 16B 1.8V DUAL 32QFN
Manufacturer
Exar Corporation
Type
Dual UART with 16-byte FIFOsr
Datasheet
1.XR16M2550IL32-F.pdf
(47 pages)
Specifications of XR16M2550IL32-F
Number Of Channels
2, DUART
Package / Case
32-VFQFN Exposed Pad
Features
*
Fifo's
16 Byte
Voltage - Supply
2.25 V ~ 3.6 V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Data Rate
16 Mbps
Supply Voltage (max)
3.63 V
Supply Voltage (min)
1.62 V
Supply Current
0.5 mA to 2 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 45 C
Mounting Style
SMD/SMT
Operating Supply Voltage
1.62 V to 3.63 V
No. Of Channels
2
Uart Features
Two Independent UART Channels, Device Identification & Revision
Supply Voltage Range
1.62V To 3.63V
Operating Temperature Range
-40°C To +85°C
Rohs Compliant
Yes
Digital Ic Case Style
QFN
No. Of Pins
32
Filter Terminals
SMD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
1016-1285
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XR16M2550IL32-F
Manufacturer:
ADI
Quantity:
469
Part Number:
XR16M2550IL32-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
XR16M2550
HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO
EFR[5]: Special Character Detect Enable
•
•
EFR[6]: Auto RTS Flow Control Enable
RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is
selected, an interrupt will be generated when the receive FIFO is filled to the selected trigger level and RTS de-
asserts HIGH at the next upper trigger level. RTS# will return LOW when FIFO data falls below the next lower
trigger level. The RTS# output must be asserted (LOW) before the auto RTS can take effect. RTS# pin will
function as a general purpose output when hardware flow control is disabled.
•
•
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS Flow Control.
•
•
These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2.
For more details, see
4.14.1
Logic 0 = Special Character Detect Disabled (default).
Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set
to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If
flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= ‘10’) then flow control and special character work
normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]= ‘01’) then flow control works
normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character
interrupt, if enabled via IER bit-5.
Logic 0 = Automatic RTS flow control is disabled (default).
Logic 1 = Enable Automatic RTS flow control.
Logic 0 = Automatic CTS flow control is disabled (default).
Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts HIGH.
Data transmission resumes when CTS# returns LOW.
Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write
Table
7.
34
REV. 1.0.2