XR16M2550IL32-F Exar Corporation, XR16M2550IL32-F Datasheet - Page 42

• Manufacturer Part Number: XR16M2550IL32-F
• Description: IC UART FIFO 16B 1.8V DUAL 32QFN
• Manufacturer: Exar Corporation
• Type: Dual UART with 16-byte FIFOsr

Specifications of XR16M2550IL32-F

• Number Of Channels: 2, DUART
• Package / Case: 32-VFQFN Exposed Pad
• Features: *
• Fifo's: 16 Byte
• Voltage - Supply: 2.25 V ~ 3.6 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 16 Mbps
• Supply Voltage (max): 3.63 V
• Supply Voltage (min): 1.62 V
• Supply Current: 0.5 mA to 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 45 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.62 V to 3.63 V
• No. Of Channels: 2
• Uart Features: Two Independent UART Channels, Device Identification & Revision
• Supply Voltage Range: 1.62V To 3.63V
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Digital Ic Case Style: QFN
• No. Of Pins: 32
• Filter Terminals: SMD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1285

XR16M2550
HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO
F
F
IGURE
IGURE
(Unloading)
(Unloading)
(Loading data
(Loading data
*INT cleared when the ISR is read or when TX FIFO fills up to trigger level.
*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.
21. T
22. T
into FIFO)
into FIFO)
TX
INT*
TXRDY#
IOW#
TX
INT*
TXRDY#
IOW#
RANSMIT
RANSMIT
TX FIFO
enabled
Empty
enabled
IER[1]
IER[1]
TX FIFO
Data in
Start
Bit
S
R
R
D0:D7
EADY
EADY
ISR Read
Stop
Bit
T
Start
& I
Bit
& I
ISR is read
S
S
T
D0:D7
D0:D7
NTERRUPT
NTERRUPT
WT
TX FIFO fills up
to trigger level
TX FIFO fills up
to trigger level
Stop
Bit
T
T
T
T
S
IMING
IMING
D0:D7
D0:D7
[FIFO M
[FIFO M
T
S
S
TX FIFO
42
Full
D0:D7
D0:D7
T
T
WRI
WRI
ODE
ODE
T
T
, DMA M
, DMA M
T
T
SRT
SI
T
S
S
D0:D7
D0:D7
ODE
below trigger level
ODE
T
TX FIFO drops
WT
T
T
D
E
S
S
NABLED
ISABLED
ISR is read
D0:D7
D0:D7
below trigger level
TX FIFO drops
T
T
]
T
SI
]
empty location
FOR
FOR
At least 1
in FIFO
ISR Read
C
C
S
S
HANNELS
Last Data Byte
Last Data Byte
HANNELS
Transmitted
Transmitted
D0:D7
D0:D7
TXDMA#
TX FIFO
TXDMA
Empty
T
SRT
T
T
REV. 1.0.2
A & B
A & B