XR88C681CP/40-F Exar Corporation, XR88C681CP/40-F Datasheet - Page 53

• Manufacturer Part Number: XR88C681CP/40-F
• Description: IC UART CMOS DUAL 40PDIP
• Manufacturer: Exar Corporation
• Type: CMOS Dual Channel UARTr

Specifications of XR88C681CP/40-F

• Number Of Channels: 2, DUART
• Package / Case: 40-DIP (0.600", 15.24mm)
• Features: *
• Fifo's: 1 Byte, 3 Byte
• Voltage - Supply: 5V
• With Parallel Port: Yes
• With Cmos: Yes
• Mounting Type: Through Hole
• Data Rate: 1 Mbps
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Supply Current: 15 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Operating Supply Voltage: 5 V
• Propagation Delay Time Ns: 400 ns
• No. Of Channels: 2
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Filter Terminals: DIP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1328-5

D.2 Bit Rate Generator
The BRG (Bit Rate Generator) accepts the timing output
of the Oscillator Circuit and generate the clock signal for
23 commonly used data communication bit rates ranging
from 50 bps up to 115.2kbps. Please note that the BRG
will only generate these standard bit rates if the Oscillator
Circuit is running at 3.6864 MHz. Additionally, the actual
Rev. 2.11
X1/CLK
Figure 27. Block Diagram of the Bit Rate Generator portion of the Timing Control Block
X2
Oscillator
Circuit
Bit Rate Generator
Channels A and B
ACR[7]
53
clock frequencies output from the BRG are at 16 times
these rates.
The user can select one of two different sets of bit rates, to
be generated from the BRG. This selection is made by
setting or clearing ACR[7]. A listing of these sets of Bit
Rates, from the BRG, is presented in the discussion of the
Clock Select Registers (CSRs) in Section D.5. A block
diagram of the BRG circuitry is presented in Figure 27.
CSRA[7:4]
32:1 MUX
CSRB[3:0]
32:1 MUX
CSRA[3:0]
32:1 MUX
CSRB[7:4]
32:1 MUX
XR88C681
RXCA
TXCA
TXCB
RXCB