XR88C681CP/40-F Exar Corporation, XR88C681CP/40-F Datasheet - Page 63

• Manufacturer Part Number: XR88C681CP/40-F
• Description: IC UART CMOS DUAL 40PDIP
• Manufacturer: Exar Corporation
• Type: CMOS Dual Channel UARTr

Specifications of XR88C681CP/40-F

• Number Of Channels: 2, DUART
• Package / Case: 40-DIP (0.600", 15.24mm)
• Features: *
• Fifo's: 1 Byte, 3 Byte
• Voltage - Supply: 5V
• With Parallel Port: Yes
• With Cmos: Yes
• Mounting Type: Through Hole
• Data Rate: 1 Mbps
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Supply Current: 15 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Operating Supply Voltage: 5 V
• Propagation Delay Time Ns: 400 ns
• No. Of Channels: 2
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Filter Terminals: DIP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1328-5

E.2 Input Port Configuration Registers (IPCR)
Change of state detectors are provided for input pins IP0 through IP3. These inputs are sampled by the 38.4kHz output
of the BRG (2.4kbps x 16). A high-to-low or low-to-high transition at these input lasting at least two clock periods
(approximately 50 s) will guarantee that the corresponding bit in the input port change register (IPCR) will be set,
although it may be set by a change of state as short as 25 s. The bit format of the IPCR follows. The status bits in the
IPCR (IPCR[7:4]) are cleared when the register is read by the CPU. Any change of state can also be programmed to
generate an interrupt via the “Input Port Change of State” interrupt.
Delta IP3
1 = Yes
0 = No
Rev. 2.11
Input Port
Bit 7
IP0
IP1
IP2
IP3
IP4
IP5
Delta IP2
1 = Yes
0 = No
Bit 6
-
Note: this input is Active Low, for the CTS function
-
Note: This input is Active Low for the CTS function
CT_EX: Counter/Timer External Clock Input.
RXCB: External Clock input for Receiver
Channel B
TXCA: External Clock input for Transmitter
Channel A
RXCA: External Clock input for Receiver
Channel A
TXCB: External Clock input for Transmitter
Channel B
CTSA: Clear to Send (CTS) input for Channel A.
CTSB: Clear to Send (CTS) input for Channel B.
Table 21. Listing of Alternate Function for the Input Port
Table 22. Input Port Configuration Register - IPCR
Delta IP1
1 = Yes
Alternate Function(s)
0 = No
Bit 5
Delta IP0
1 = Yes
0 = No
Bit 4
63
1 = High
0 = Low
Bit 3
IP3
IP0 can be programmed to function as the
input by setting MR2A[4] =1. For a more detailed
discussion on this function, please see Section
G.3.
IP1 can be programmed to function as the
input by setting MR2B[4] =1. For a more detailed
discussion on this function, please see Section G.3.
IP2 can be programmed to function as the external
clock input for the Counter/Timer by setting
ACR[6:4] = [0, 0, 0]. For a more detailed discus-
sion into the effect of this action please see Section
D.2
IP2 can also be programmed to function as the
external clock input for the Receiver of Channel B
by setting CSRB[7:4] = [1, 1, 1, 0] for the 16X
Clock, or CSRB[7:4] = [1, 1, 1, 1] for the 1X Clock.
IP3 can be programmed to function as the external
clock input for the Transmitter of Channel A by set-
ting CSRA[3:0] = [1, 1, 1, 0] for the 16X Clock, or
CSRA[3:0] = [1, 1, 1, 1] for the 1X Clock.
IP4 can be programmed to function as the external
clock input for the Receiver of Channel A by setting
CSRA[7:4] = [1, 1, 1, 0] for the 16X Clock, or
CSRA[7:4] = [1, 1, 1, 1] for the 1X Clock.
IP5 can be programmed to function as the external
clock input for the Transmitter of Channel B by set-
ting CSRB[3:0] = [1, 1, 1, 0] for the 16X Clock, or
CSRB[3:0] = [1, 1, 1, 1] for the 1X Clock.
Approach to Program Alternate Functions
1 = High
0 = Low
Bit 2
IP2
XR88C681
1 = High
0 = Low
Bit 1
IP1
1 = High
0 = Low
Bit 0
-
IP0
-
CTSB
CTSA