XR88C681CP/40-F Exar Corporation, XR88C681CP/40-F Datasheet - Page 7

• Manufacturer Part Number: XR88C681CP/40-F
• Description: IC UART CMOS DUAL 40PDIP
• Manufacturer: Exar Corporation
• Type: CMOS Dual Channel UARTr

Specifications of XR88C681CP/40-F

• Number Of Channels: 2, DUART
• Package / Case: 40-DIP (0.600", 15.24mm)
• Features: *
• Fifo's: 1 Byte, 3 Byte
• Voltage - Supply: 5V
• With Parallel Port: Yes
• With Cmos: Yes
• Mounting Type: Through Hole
• Data Rate: 1 Mbps
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Supply Current: 15 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Operating Supply Voltage: 5 V
• Propagation Delay Time Ns: 400 ns
• No. Of Channels: 2
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Filter Terminals: DIP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1328-5

44 PLCC
Rev. 2.11
38
39
40
41
41
42
42
43
43
44
40 PDIP,
CDIP
34
35
36
37
37
38
38
39
39
40
28 PDIP
25
26
27
28
(C/T_EX)
(Z-Mode)
(Z-Mode)
Symbol
(RXCB)
(RXCA)
RESET
(TXCB)
-IACK
V
-CS
IEO
IP2
IP6
IP5
IP4
IEI
CC
PWR
Type
O
I
I
I
I
I
I
I
I
7
Description
Master Reset (Active High). Asserting this input clears in-
ternal registers, SR, ISR, IMR, OPR, OPCR, and initializes
the IVR to 0F16. Asserting this input also stops the Counter/
Timer, puts OP0 - OP7 in the high state, and places both
serial channels in the inactive state with TXDA and TXDB
outputs marking (high).
Chip Select (Active Low). The data bus is tri-stated when
-CS is “high.” Data transfers between the CPU and the
DUART via D0 - D7 are enabled when -CS is “low”.
Input 2. (General Purpose Input). This input pin can also
be programmed to function as the “Counter/Timer external
clock” input (C/T_EX).
Input 6 (I-Mode). General Purpose Input pin. This input pin
can also be programmed to function as the External Receiv-
er Clock for Channel B (RXCB).
Interrupt Acknowledge Input (Z-Mode). Active Low.
This input is the CPU’s response to the Interrupt Request
issued by the DUART device. When the CPU asserts this
input, it indicates that the DUART’s interrupt request is about
to be serviced, and that the very next cycle will be an Inter-
rupt Acknowledge Cycle. The DUART will respond to the
CPU’s Interrupt Acknowledge by placing the contents of the
Interrupt Vector Register (IVR) on the data bus (D0 - D7).
Input 5 (I-Mode). General Purpose Input pin. This pin can
also be configured to function as the external clock input for
the Transmitter of Channel B (TXCB).
Interrupt Enable Output (Z-Mode). Active High.
This output pin is normally “high”. However, either of the
following two conditions can cause this output pin to be ne-
gated (toggled “low”).
1. If the IEI (Interrupt Enable Input) pin is “low”. If IEO is
2. The DUART has issued an Interrupt Request to the CPU
Input 4 (I-Mode). General Purpose Input pin. This input pin
can also be configured to function as the external clock input
for the Receiver of Channel A (RXCA).
Interrupt Enable Input (Z-Mode). Active High.
If this active-high input is at a logic “high”, the DUART is ca-
pable of generating all non-masked Interrupt Requests to the
CPU. If this input is at a logic “low”, the DUART is inhibited
from generating any Interrupt Requests to the CPU.
Most Positive Power Supply.
“low” because of the IEI pin, IEO will toggle “high” once
the IEI has toggled “high”.
(-INTR pin is toggled “low”). If IEO is “low” because the
DUART has requested an Interrupt, then IEO will remain
“low”, throughout the Interrupt Service Routine, until the
CPU has invoked the “” command.
XR88C681