XR88C681CP/40-F Exar Corporation, XR88C681CP/40-F Datasheet - Page 59

• Manufacturer Part Number: XR88C681CP/40-F
• Description: IC UART CMOS DUAL 40PDIP
• Manufacturer: Exar Corporation
• Type: CMOS Dual Channel UARTr

Specifications of XR88C681CP/40-F

• Number Of Channels: 2, DUART
• Package / Case: 40-DIP (0.600", 15.24mm)
• Features: *
• Fifo's: 1 Byte, 3 Byte
• Voltage - Supply: 5V
• With Parallel Port: Yes
• With Cmos: Yes
• Mounting Type: Through Hole
• Data Rate: 1 Mbps
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Supply Current: 15 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Operating Supply Voltage: 5 V
• Propagation Delay Time Ns: 400 ns
• No. Of Channels: 2
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Filter Terminals: DIP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1328-5

In general the bit-error-rate, for this “uncorrected” system
is a function of the timing differences between the TX and
RX local clock signals. However, in order to correct for
Receiver Drift and to minimize the BER during serial data
transmission, many UARTs in the market place, employ
Receiver Oversampling of the START bit. When this
feature is employed, the Receiver, upon detection of the
START bit, will begin oversampling this START bit by
some integer factor. Typically, for most present day
UARTs, this over-sample factor is 16. (The XR88C681
device also accommodates 16X receiver oversampling of
the START bit). Therefore, in these devices, when the
Receiver detects the occurrence of a START bit, it (the
Receiver) will begin oversampling this START bit by a
Rev. 2.11
Figure 32. The Typical Sampling Pattern of Each Receiver Within the XR88C681 Device.
7- 16X clock
periods
the Midpoint
Chosen as
of the Bit
1 Bit Period
59
factor of 16. However, after 7 16X clock periods has
elapsed, the receiver will assume this point (within the
START bit) to be the mid point of the bit period, and will
cease oversampling of the START bit and of the
subsequent data. From this point, through the end of the
character, the Receiver will sample the serial data stream
at the 1X rate. Stated another way, once the Receiver has
reached, what it believes to be the mid-point of the START
bit, the receiver will, from that point, begin sampling the
serial data at 1-bit period interval (see Figure 32). After
the Receiver has received the STOP bit, it will await the
occurrence of the START bit. Once the START bit has
been detected, this oversampling procedure is repeated.
XR88C681