ATA5724P3-TKQY Atmel, ATA5724P3-TKQY Datasheet - Page 20

• Manufacturer Part Number: ATA5724P3-TKQY
• Description: IC RCVR ASK/FSK UHF 20-SSOP
• Manufacturer: Atmel

Specifications of ATA5724P3-TKQY

• Frequency: 433MHz
• Sensitivity: -113dBm
• Data Rate - Maximum: 10 kbps
• Modulation Or Protocol: ASK, FSK
• Applications: General Purpose
• Current - Receiving: 11mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SOIC (0.200", 5.30mm Width)
• Operating Temperature (min): -40C
• Operating Temperature (max): 105C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 4.4mm
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant

20
ATA5723/ATA5724/ATA5728
Use the function of the data clock only in conjunction with the bit check 3, 6 or 9 is recom-
mended. If the bit check is set to 0 or the receiver is set to receiving mode using the pin
POLLING/_ON, the data clock is available if the data clock control logic has detected the dis-
tance 2T (Start bit).
Note that for Bi-phase-coded signals, the data clock is issued at the end of the bit.
Figure 9-1.
Figure 9-2.
Data_out (DATA)
Data_out (DATA)
DATA_CLK
DATA_CLK
Dem_out
Dem_out
Timing Diagram of the Data Clock
Data Clock Disappears Because of a Timing Error
'1'
'1'
Bit-check mode
data clock control
Timing error
Receiving mode,
Bit check ok
logic active
'1'
'1'
'1'
'1'
Preburst
T
ee
'1'
'1'
T
ee
< T
T
'1'
'1'
Lim_min
2T
Start bit
or T
'0'
'0'
Data
Receiving mode,
Lim_max
bit check active
data clock control logic active
'1'
'1'
< T
Receiving mode,
ee
'1'
'1'
< T
t
Lim_min_2T
Delay
'0'
'0'
Data
or T
'1'
'1'
ee
9106E–RKE–07/08
t
> T
P_Data_Clk
Lim_max_2T
'0'
'0'