JN5139-Z01-V NXP Semiconductors, JN5139-Z01-V Datasheet - Page 51

• Manufacturer Part Number: JN5139-Z01-V
• Description: IC MCU ZIGBEE 32BIT 2.4G 56QFN
• Manufacturer: NXP Semiconductors
• Series: JN5139-Z01Rxr

Specifications of JN5139-Z01-V

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3dBm
• Sensitivity: -97dBm
• Voltage - Supply: 2.2 V ~ 3.6 V
• Current - Receiving: 34mA
• Current - Transmitting: 34mA
• Data Interface: PCB, Surface Mount
• Memory Size: 96kB RAM, 192kB ROM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Rate - Maximum: -
• Other names: 616-1034-2; 935293943515; JN5139-Z01-AI; JN5139-Z01-V; JN5139-Z01R1-ARV; JN5139-Z01R1V

Whilst in CPU doze the current associated with the CPU drops, the RAM_FRACTION and ROM_FRACTION are both
0 and hence the base device current consumption drops to 2.85mA.
16.3 Sleep Mode
The JN5139 enters sleep mode through software control. In this mode most of the internal chip functions are
shutdown to save power, however the state of DIO pins are retained, including the output values and pull-up enables,
and this therefore preserves any interface to the outside world. The DAC outputs are placed into a high impedance
state.
When entering into sleep mode, there is an option to retain the RAM contents throughout the sleep period. If the
wakeup timers are not to be used for a wakeup event and the application does not require them to run continually,
then power can be saved by switching off the 32kHz oscillator if selected as the system clock through software
control. The oscillator will be restarted when a wakeup event occurs.
Whilst in sleep mode one of three possible events can cause a wakeup to occur: transitions on DIO inputs, expiry of
wakeup timers or comparator events. If any of these events occur, and the relevant interrupt is enabled, then an
interrupt is generated that will cause a wakeup from sleep. It is possible for multiple wakeup sources to trigger an
event at the same instant and only one of them will be accountable for the wakeup period. It is therefore necessary in
software to remove all other pending wakeup events prior to requesting entry back into sleep mode; otherwise, the
device will re-awaken immediately.
When wakeup occurs, a similar sequence of events to the reset process described in section 6.1 happens. The
16MHz oscillator is started up, once stable the CPU system is enabled and the reset is removed.
Software
determines that this is a reset from sleep and so commences with the wakeup process. If the RAM contents were
held through sleep, wakeup is quicker as the application program does not have to be reloaded from Flash memory.
See section 17.3.5 for wake up timings.
16.3.1 Wakeup Timer Event
The JN5139 contains two 32-bit wakeup timers that are counters clocked by the 32kHz system clock, and can be
programmed to generate a wake-up event. Following a wakeup event, the timers continue to run. These timers are
described in section 12.3.
Timer events can be generated from both of the two timers; one is intended for use by the 802.15.4 protocol, the
other being available for use by the Application running on the CPU. These timers are available to run at any time,
even during sleep mode.
16.3.2 DIO Event
Any DIO pin when used as an input has the capability, by detecting a transition, to generate a wake-up event. Once
this feature has been enabled the type of transition can be specified (rising or falling edge). Even when groups of
DIO lines are configured as alternative functions such as the UARTs or Timers etc, any input line in the group can still
be used to provide a wakeup event. This means that an external device communicating over the UART can wakeup
a sleeping device by asserting its RTS signal pin (which is the CTS input of the JN5139).
16.3.3 Comparator Event
The comparator can generate a wakeup interrupt when a change in the relative levels of the positive and negative
inputs occurs. The ability to wakeup when continuously monitoring analogue signals is useful in ultra-low power
applications. For example, the JN5139 can remain in sleep mode until the voltage drops below a threshold and then
be woken up to deal with the alarm condition.
16.4 Deep Sleep Mode
Deep sleep mode gives the lowest power consumption. All switchable power domains are off and certain functions in
the VDD supply power domain, including the 32kHz system clock are stopped. This mode can be exited by a power
down, a hardware reset on the RESETN pin, or a DIO event. The DIO event in this mode causes a chip reset to
occur.
© NXP Laboratories UK 2010
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