XRT94L43IB-F Exar Corporation, XRT94L43IB-F Datasheet - Page 109
XRT94L43IB-F
Manufacturer Part Number
XRT94L43IB-F
Description
IC MAPPER SONET/SDH OC12 516BGA
Manufacturer
Exar Corporation
Datasheet
1.XRT94L43IB.pdf
(328 pages)
Specifications of XRT94L43IB-F
Applications
Network Switches
Interface
Bus
Voltage - Supply
2.5V, 3.3V
Package / Case
516-BBGA
Mounting Type
Surface Mount
Product
Mapper
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
XRT94L43IB-F
Manufacturer:
Exar Corporation
Quantity:
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Part Number:
XRT94L43IB-F
Manufacturer:
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STS-3/STM-1 TELECOM BUS INTERFACE - RECEIVE DIRECTION
XRT94L43
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
P
D21
IN
#
STS3RxD_D_0_4
DS3/E3/
STS1_Data_OUT_
8
RxSBData_4
S
IGNAL
N
AME
I/O
O
S
CMOS Receive STS-3/STM-1 Telecom Bus - Channel 0 - Output Data Bus
T
IGNAL
YPE
Pin Number 4/DS3/E3 Framer or Transmit STS-1 TOH Processor
block line interface output Pin - Channel 8 (DS3/E3/
STS1_DATA_OUT_8):
The function of this output pin depends upon whether or not theSTS-3/
STM-1 Telecom Bus Interface, associated with Channel 0 is enabled.
If STS-3/STM-1 Telecom Bus (Channel 0) has been enabled - STS-3/
STM-1 Receive Telecom Bus - Output Data bus Pin Number 4:
STSRxD_D_0_4:
This output pin along with STS3RxD_D_0[7:5] and STS3RxD_D_0[3:0]
function as the STS-3/STM-1 Receive (Drop) Telecom Bus - Output Data
Bus for Channel 0. The STS-3/STM-1 Telecom Bus Interface will update
the data via this output upon the rising edge of STS3RxD_CLK_0.
If STS-3/STM-1 Telecom Bus (Channel 0) is disabled - DS3/E3/
STS1_DATA_OUT Line Interface Data output Pin - Channel 8:
This pin outputs single-rail DS3, E3 or STS-1 data to a DS3/E3/STS-1
LIU IC. This output pin should be connected to the TPOS/TDATA input of
the DS3/E3/STS-1 LIU IC (corresponding to Channel 8). By default, the
data that is being output via this output pin will be updated upon the rising
edge of the DS3/E3/STS-1_CLK_OUT_8 signal pin number C24.
For DS3/E3 Applications
The XRT94L43 can be configured to update the DS3/E3/STS1_DATA_8
output signal upon the falling edge of the DS3/E3/STS1_CLK_8 signal by
setting Bit 2 (DS3/E3/STS1_CLK_OUT Invert), within the I/O Control
Register - Channel 8 (Indirect Address = 0x9E, 0x01), (Direct Address =
0x9F01) to a "1".
For STS-1 Applications
The XRT94L43 can not be configured to update the DS3/E3/
STS1_DATA_OUT_8 signal upon the falling edge of DS3/E3/
STS1_CLK_OUT_8.
103
D
ESCRIPTION
REV. 1.0.2
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