XRT94L43IB-F Exar Corporation, XRT94L43IB-F Datasheet - Page 45
XRT94L43IB-F
Manufacturer Part Number
XRT94L43IB-F
Description
IC MAPPER SONET/SDH OC12 516BGA
Manufacturer
Exar Corporation
Datasheet
1.XRT94L43IB.pdf
(328 pages)
Specifications of XRT94L43IB-F
Applications
Network Switches
Interface
Bus
Voltage - Supply
2.5V, 3.3V
Package / Case
516-BBGA
Mounting Type
Surface Mount
Product
Mapper
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
XRT94L43IB-F
Manufacturer:
Exar Corporation
Quantity:
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Part Number:
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Manufacturer:
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XRT94L43
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
STS-3/STM-1 TELECOM BUS INTERFACE - TRANSMIT DIRECTION
AF17
P
IN
#
STS3TxA_C1J1_3
ING_LCV_IN_11
ING_RxNEG_IN_11
TxSTS1PL_11
TxSBFrame_3
S
IGNAL
N
AME
I/O
I/O
S
CMOS
T
TTL/
IGNAL
YPE
STS-3/STM-1 Transmit Telecom Bus C1/J1 Byte Phase Indicator
Input Signal (Channel 3); DS3/E3 Frame Generator Framing
Pulse Input/Output Pin - Channel 11:
The function of this pin depends upon whether or not theSTS-3/STM-
1 Telecom Bus Interface for Telecom Bus Channel 3 has been
enabled.
If STS-3/STM-1 Telecom Bus (Telecom Bus Channel 3) has been
enabled - STS-3/STM-1 Transmit Telecom Bus C1/J1 Byte Phase
Indicator Input Signal (Channel 3):
This input pin should be pulsed "High" during both of the following
conditions.
If STS-3/STM-1 Telecom Bus (Channel 3) is disabled - DS3/E3
Framer Block LCV/RxNEG Input - Channel 11)
:If the STS-3/STM-1 Telecom Bus (Channel 3) is disabled and if the
DS3/E3 Framer block (associated with Channel 11) is enabled then
this pin will function as either an LCV or an RxNEG input pin.
If Channel 11 is configured to operate in the Single- Rail Mode,
and if the Primary Frame Synchronizer block is configured to
operate in the Ingress Path - ING_LCV_IN_11 Input pin:
If the Primary Frame Synchronizer Block (associated with Channel
11) is configured to operate in the Ingress Path, and if Channel 11 is
configured to operate in the Single-Rail Mode, then this input pin will
function as the "LCV" (Line Code Violation) input pin. In this case,
the user should connect this particular input pin to the "LCV" output
pin of the corresponding DS3/E3/STS-1 LIU Channel.
If Channel 11 is configured to operate in the Dual-Rail Mode, and
if the Primary Frame Synchronizer block is configured to oper-
ate in the Ingress Path - ING_RxNEG_IN_11:
If the Primary Frame Synchronizer block (associated with Channel
11) is configured to operate in the Ingress Path, and if Channel 8 is
configured to operate in the Dual-Rail Mode, then this input pin will
function as the "RxNEG" (Negative Polarity Data) input pin. In this
case, the user should connect this particular input to the "RxNEG"
output pin of the corresponding DS3/E3/STS-1 LIU Channel.
N
OTE
1. Whenever the C1 byte is being input to the STS-3/STM-1
2. Whenever the J1 byte is being input to the STS-3/STM-1
: This pin is inactive if the Primary Frame Synchronizer block
Transmit Telecom Bus (TXA_D_3[7:0]) input pins.
Transmit Telecom Bus (TXA_D_3[7:0]) input pins.
39
(associated with Channel 11) is NOT configured to operate
in the Ingress Path.
D
ESCRIPTION
REV. 1.0.2
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