XRT94L43IB-F Exar Corporation, XRT94L43IB-F Datasheet - Page 259

• Manufacturer Part Number: XRT94L43IB-F
• Description: IC MAPPER SONET/SDH OC12 516BGA
• Manufacturer: Exar Corporation

Specifications of XRT94L43IB-F

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 2.5V, 3.3V
• Package / Case: 516-BBGA
• Mounting Type: Surface Mount
• Product: Mapper
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L43
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
STS-3/STM-1 TELECOM BUS INTERFACE - RECEIVE DIRECTION
P
G26
IN
#
STS3RxD_D_1_5
DS3/E3/STS1_Clk_OUT_1
RxSBData_5
S
IGNAL
N
AME
I/O
O
S
CMOS Receive STS-3/STM-1 Telecom Bus - Channel 1 - Output
T
IGNAL
YPE
Data Bus Pin Number 5/DS3/E3 Framer or Transmit STS-1
TOH Processor block line interface clock output Pin -
Channel 1: (DS3/E3/STS1_CLK_OUT_1):
The function of this output pin depends upon whether or not
theSTS-3/STM-1 Telecom Bus Interface, associated with
Channel 1 is enabled.
If STS-3/STM-1 Telecom Bus (Channel 1) has been enabled
- STS-3/STM-1 Receive Telecom Bus - Output Data bus Pin
Number 5: STSRxD_D_1_5:
This output pin along with STS3RxD_D_1[7:6] and
STS3RxD_D_1[4:0] function as the STS-3/STM-1 Receive
(Drop) Telecom Bus - Output Data Bus for Channel 1. The
STS-3/STM-1 Telecom Bus Interface will update the data via
this output upon the rising edge of STS3RxD_CLK_1.
If STS-3/STM-1 Telecom Bus (Channel 1) is disabled - DS3/
E3/STS1_CLK_OUT Line Interface Clock output Pin -
Channel 1:
This pin outputs a DS3, E3 or STS-1 rate clock signal to a DS3/
E3/STS-1 LIU IC. This output pin should be connected to the
TxCLK input of the DS3/E3/STS-1 LIU IC (corresponding to
Channel 1).
By default, the data, which is being output via the DS3/E3/
STS1_DATA_OUT_1 output pin will be updated upon the rising
edge of this clock output signal.
For DS3/E3 Applications
The XRT94L43 can be configured to update the DS3/E3/
STS1_DATA_1 output signal upon the falling edge of the DS3/
E3/STS1_CLK_1 signal by setting Bit 0 (DS3/E3/
STS1_CLK_OUT Invert), within the I/O Control Register -
Channel 1 (Indirect Address = 0x2E, 0x01), (Direct Address =
0x2F01) to a "1".
For STS-1 Applications
The XRT94L43 can not be configured to update the DS3/E3/
STS1_DATA_OUT_1 signal upon the falling edge of DS3/E3/
STS1_CLK_1.
253
D
ESCRIPTION
REV. 1.0.2