XRT94L43IB-F Exar Corporation, XRT94L43IB-F Datasheet - Page 272

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XRT94L43IB-F

Manufacturer Part Number
XRT94L43IB-F
Description
IC MAPPER SONET/SDH OC12 516BGA
Manufacturer
Exar Corporation
Datasheet

Specifications of XRT94L43IB-F

Applications
Network Switches
Interface
Bus
Voltage - Supply
2.5V, 3.3V
Package / Case
516-BBGA
Mounting Type
Surface Mount
Product
Mapper
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Part Number
Manufacturer
Quantity
Price
Part Number:
XRT94L43IB-F
Manufacturer:
Exar Corporation
Quantity:
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Part Number:
XRT94L43IB-F
Manufacturer:
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Quantity:
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REV. 1.0.2
STS-3/STM-1 TELECOM BUS INTERFACE - RECEIVE DIRECTION
AB21
P
IN
#
STS3RxD_D_3_2
DS3/E3/
STS1_Data_OUT_3
RxSBData_2
S
IGNAL
N
AME
I/O
O
S
CMOS Receive STS-3/STM-1 Telecom Bus - Channel 3 - Output
T
IGNAL
YPE
Data Bus Pin Number 2/DS3/E3 Framer or Transmit STS-1
TOH Processor block line interface output Pin - Channel 3
(DS3/E3/STS1_DATA_OUT_3):
The function of this output pin depends upon whether or not
theSTS-3/STM-1 Telecom Bus Interface, associated with
Channel 3 is enabled.
If STS-3/STM-1 Telecom Bus (Channel 3) has been enabled
- STS-3/STM-1 Receive Telecom Bus - Output Data bus Pin
Number 2: STSRxD_D_3_2:
This output pin along with STS3RxD_D_3[7:3] and
STS3RxD_D_3[1:0] function as the STS-3/STM-1 Receive
(Drop) Telecom Bus - Output Data Bus for Channel 3. The
STS-3/STM-1 Telecom Bus Interface will update the data via
this output upon the rising edge of STS3RxD_CLK_3.
If STS-3/STM-1 Telecom Bus (Channel 3) is disabled - DS3/
E3/STS1_DATA_OUT Line Interface Data output Pin -
Channel 3.
This pin outputs single-rail DS3, E3 or STS-1 data to a DS3/E3/
STS-1 LIU IC. This output pin should be connected to the
TPOS/TDATA input of the DS3/E3/STS-1 LIU IC (correspond-
ing to Channel 3). By default, the data that is output via this pin
will be updated upon the rising edge of the DS3/E3/
STS1_CLK_OUT_3 signal pin number AB20.
For DS3/E3 Applications
The XRT94L43 can be configured to update this output signal
upon the falling edge of the DS3/E3/STS1_CLK_3 signal by
setting Bit 2 (DS3/E3/STS1_CLK_OUT Invert), within the I/O
Control Register - Channel 3 (Indirect Address = 0x4E, 0x01),
(Direct Address = 0x4F01) to a "1".
For STS-1 Applications
The XRT94L43 can not be configured to update the DS3/E3/
STS1_DATA_OUT_3 signal upon the falling edge of DS3/E3/
STS1_CLK_OUT_3.
266
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
D
ESCRIPTION
XRT94L43

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