FDS8449_F085 Fairchild Semiconductor, FDS8449_F085 Datasheet - Page 2

MOSFET N-CH 40V 7.6A 8-SOIC

FDS8449_F085

Manufacturer Part Number
FDS8449_F085
Description
MOSFET N-CH 40V 7.6A 8-SOIC
Manufacturer
Fairchild Semiconductor
Series
PowerTrench®r
Datasheet

Specifications of FDS8449_F085

Fet Type
MOSFET N-Channel, Metal Oxide
Fet Feature
Logic Level Gate
Rds On (max) @ Id, Vgs
29 mOhm @ 7.6A, 10V
Drain To Source Voltage (vdss)
40V
Current - Continuous Drain (id) @ 25° C
7.6A
Vgs(th) (max) @ Id
3V @ 250µA
Gate Charge (qg) @ Vgs
11nC @ 10V
Input Capacitance (ciss) @ Vds
760pF @ 20V
Power - Max
1W
Mounting Type
Surface Mount
Package / Case
8-SOIC (0.154", 3.90mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
FDS8449_F085FDS8449-F085P
Manufacturer:
ON/安森美
Quantity:
20 000
FDS8449_F085 Rev. A
E
I
Notes:
1. R
2 Test: Pulse Width < 300μs, Duty Cycle < 2.0%
3. BV(avalanche) Single-Pulse rating is guaranteed if device is operated within the UIS SOA boundary of the device.
Electrical Characteristics
Symbol
Drain-Source Avalanche Ratings
Off Characteristics
BV
ΔBV
I
I
On Characteristics
V
ΔV
R
g
Dynamic Characteristics
C
C
C
Switching Characteristics
t
t
t
Q
Q
Q
Drain–Source Diode Characteristics
V
t
Q
t
AS
DSS
GSS
d(on)
r
d(off)
rr
f
R
AS
FS
GS(th)
SD
the drain pins. R
ΔT
ΔT
DS(on)
iss
oss
rss
g
gs
gd
rr
G
θJA
GS(th)
DSS
DSS
J
J
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
Drain-Source Avalanche Energy
Drain-Source Avalanche Current
Drain–Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate–Body Leakage
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
Turn–On Delay Time
Turn–On Rise Time
Turn–Off Delay Time
Turn–Off Fall Time
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
Drain–Source Diode Forward
Voltage
Diode Reverse Recovery Time
Diode Reverse Recovery Charge
θJC
is guaranteed by design while R
Parameter
(Note 2)
a)
(Note 2)
50°C/W when mounted
on a 1in
copper
θCA
is determined by the user's board design.
2
pad of 2 oz
(Note 3)
T
V
V
I
V
V
V
I
V
V
V
V
V
f = 1.0 MHz
f = 1.0 MHz
V
V
V
V
V
I
A
D
D
F
DD
= 25°C unless otherwise noted
GS
DS
GS
DS
GS
GS
GS
DS
DS
DD
GS
DS
GS
GS
= 7.6 A,
= 250 μA, Referenced to 25°C
= 250 μA, Referenced to 25°C
= 10 V, I
= 40 V,
= 0 V,
= 32 V,
= ±20 V,
= V
= 10 V,
= 4.5 V,
= 10 V,
= 20 V,
= 20 V,
= 10 V,
= 20 V,
= 5 V
= 0 V,
Test Conditions
GS
,
2
D
I
= 7.6 A, T
D
I
I
V
V
D
I
I
I
V
I
R
I
I
d
= 7.3 A, L = 1 mH
D
D
D
D
D
D
S
iF
GS
DS
GEN
= 250 μA
GS
= 2.1 A
= 250 μA
= 7.6 A
= 6.8 A
= 7.6 A
= 1 A,
= 7.6 A,
/d
= 0 V
= 0 V
t
= 0 V,
= 6 Ω
= 100 A/µs
J
=125°C
(Note 2)
Min
40
1
b) 125°C/W when mounted on a
Scale 1 : 1 on letter size paper
minimum pad.
Typ
0.76
760
100
7.3
1.2
1.9
7.7
2.4
2.8
34
–5
21
26
29
21
60
23
17
9
5
3
7
Max Units
±100
1.2
27
29
36
43
18
10
17
11
1
3
6
www.fairchildsemi.com
mV/°C
mV/°C
mJ
pF
nC
nC
μA
nA
pF
Ω
nC
nS
nC
pF
ns
ns
ns
ns
A
V
V
S
V

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