ATMEGA32A-ANR Atmel, ATMEGA32A-ANR Datasheet - Page 103
![IC MCU AVR 32K FLASH 44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA32A-ANR
Manufacturer Part Number
ATMEGA32A-ANR
Description
IC MCU AVR 32K FLASH 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA32A-MU.pdf
(353 pages)
Specifications of ATMEGA32A-ANR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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16.8
16.8.1
16.8.2
8155C–AVR–02/11
Modes of Operation
Normal Mode
Clear Timer on Compare Match (CTC) Mode
A change of the COM1x1:0 bits state will have effect at the first compare match after the bits are
written. For non-PWM modes, the action can be forced to have immediate effect by using the
FOC1x strobe bits.
The mode of operation, that is, the behavior of the Timer/Counter and the output compare pins,
is defined by the combination of the Waveform Generation mode (WGM13:0) and Compare Out-
put mode (COM1x1:0) bits. The Compare Output mode bits do not affect the counting sequence,
while the Waveform Generation mode bits do. The COM1x1:0 bits control whether the PWM out-
put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes
the COM1x1:0 bits control whether the output should be set, cleared or toggle at a compare
match
For detailed timing information refer to
The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the
BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOV1) will be set in
the same timer clock cycle as the TCNT1 becomes zero. The TOV1 Flag in this case behaves
like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow
interrupt that automatically clears the TOV1 Flag, the timer resolution can be increased by soft-
ware. There are no special cases to consider in the Normal mode, a new counter value can be
written anytime.
The Input Capture unit is easy to use in Normal mode. However, observe that the maximum
interval between the external events must not exceed the resolution of the counter. If the interval
between events are too long, the timer overflow interrupt or the prescaler must be used to
extend the resolution for the capture unit.
The output compare units can be used to generate interrupts at some given time. Using the out-
put compare to generate waveforms in Normal mode is not recommended, since this will occupy
too much of the CPU time.
In Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1 Register
are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when
the counter value (TCNT1) matches either the OCR1A (WGM13:0 = 4) or the ICR1 (WGM13:0 =
12). The OCR1A or ICR1 define the top value for the counter, hence also its resolution. This
mode allows greater control of the compare match output frequency. It also simplifies the opera-
tion of counting external events.
The timing diagram for the CTC mode is shown in
increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1)
is cleared.
(See “Compare Match Output Unit” on page
“Timer/Counter Timing Diagrams” on page
102.)
Figure
16-6. The counter value (TCNT1)
ATmega32A
110.
103
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