ATMEGA64A-MNR Atmel, ATMEGA64A-MNR Datasheet - Page 310

• Manufacturer Part Number: ATMEGA64A-MNR
• Description: IC MCU AVR 64K FLASH 8QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64A-MNR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, UART, I2C
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Processor To Be Evaluated: ATMEGA64A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

27.8
27.8.1
8160C–AVR–07/09
SPI Serial Programming Pin Mapping
SPI Serial Programming Algorithm
Even though the SPI Programming interface re-uses the SPI I/O module, there is one important
difference: The MOSI/MISO pins that are mapped to PB2 and PB3 in the SPI I/O module are not
used in the Programming interface. Instead, PE0 and PE1 are used for data in SPI Program-
ming mode as shown in
Table 27-13. Pin Mapping SPI Serial Programming
Figure 27-10. SPI Serial Programming and Verify
Note:
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
When writing serial data to the ATmega64A, data is clocked on the rising edge of SCK.
When reading data from the ATmega64A, data is clocked on the falling edge of SCK. See
27-11
To program and verify the ATmega64A in the SPI Serial Programming mode, the following
sequence is recommended:
for timing details.
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
2. VCC - 0.3 < AVCC < VCC + 0.3, however, AVCC should always be within 2.7 - 5.5V.
MISO (PDO)
MOSI (PDI)
XTAL1 pin.
Symbol
SCK
Table
27-13.
MOSI
MISO
ck
ck
SCK
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
Pins
PE0
PE1
PB1
PE0
PE1
PB1
XTAL1
RESET
GND
(1)
I/O
AVCC
O
VCC
I
I
+2.7 - 5.5V
+2.7 - 5.5V
(2)
ck
ck
Serial Data Out
Serial Data In
Description
Serial Clock
ATmega64A
12 MHz
12 MHz
Figure
310