ATMEGA64A-MNR Atmel, ATMEGA64A-MNR Datasheet - Page 64

• Manufacturer Part Number: ATMEGA64A-MNR
• Description: IC MCU AVR 64K FLASH 8QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64A-MNR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, UART, I2C
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Processor To Be Evaluated: ATMEGA64A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.3
11.3.1
8160C–AVR–07/09
Register Description
MCUCR – MCU Control Register
• Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash
memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot
Loader section of the Flash. The actual address of the start of the Boot Flash section is deter-
mined by the BOOTSZ Fuses. Refer to the section
Self-programming” on page 281
tables, a special write procedure must be followed to change the IVSEL bit:
1. Write the Interrupt Vector Change Enable (IVCE) bit to one.
2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled
in the cycle IVCE is set, and they remain disabled until after the instruction following the write to
IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status
Register is unaffected by the automatic disabling.
Note:
• Bit 0 – IVCE: Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by
hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable
interrupts, as explained in the IVSEL description above. See code examples below.
Bit
0x35 (0x55)
Read/Write
Initial Value
Assembly Code Example
C Code Example
Move_interrupts:
void Move_interrupts(void)
{
}
; Enable change of Interrupt Vectors
ldi
out
; Move interrupts to boot Flash section
ldi
out
ret
/* Enable change of Interrupt Vectors */
MCUCR = (1<<IVCE);
/* Move interrupts to boot Flash section */
MCUCR = (1<<IVSEL);
If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed,
interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed
in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while
executing from the Boot Loader section. Refer to the section
Write Self-programming” on page 281
r16, (1<<IVCE)
MCUCR, r16
r16, (1<<IVSEL)
MCUCR, r16
SRE
R/W
7
0
SRW10
R/W
6
0
R/W
SE
5
0
for details. To avoid unintentional changes of Interrupt Vector
SM1
R/W
4
0
for details on Boot Lock bits.
SM0
R/W
3
0
“Boot Loader Support – Read-While-Write
SM2
R/W
2
0
“Boot Loader Support – Read-While-
IVSEL
R/W
1
0
IVCE
R/W
ATmega64A
0
0
MCUCR
64