MCF53014CMJ240J Freescale Semiconductor, MCF53014CMJ240J Datasheet - Page 37

• Manufacturer Part Number: MCF53014CMJ240J
• Description: IC MCU 32BIT 128KB 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF5301xr

Specifications of MCF53014CMJ240J

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB, USB OTG
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: Cache
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Processor Series: MCF5301x
• Core: ColdFire V3
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: I2C, UART, DSPI
• Maximum Clock Frequency: 400 KHz, 20 MHz, 25 MHz
• Number Of Timers: 4
• Operating Supply Voltage: - 0.5 V to + 2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: M53015EVB, M53017KIT, M53017MOD
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13 bit
• On-chip Dac: 16 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

5.13
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing
specs/constraints for the physical interface.
5.13.1
The following timing specs meet the requirements for both MII and 7-Wire style interfaces for a range of transceiver devices.
5.13.2
Freescale Semiconductor
1
1
In MII mode, n = 3; In RMII mode, n = 1
In MII mode, n = 3; In RMII mode, n = 1
Num
Num
E1
E2
E3
E4
E5
E6
E7
E8
Fast Ethernet AC Timing Specifications
Receive Signal Timing Specifications
Transmit Signal Timing Specifications
RXD[n:0], RXDV, RXER to RXCLK setup
RXCLK to RXD[n:0], RXDV, RXER hold
RXCLK pulse width high
RXCLK pulse width low
TXCLK to TXD[n:0], TXEN, TXER invalid
TXCLK to TXD[n:0], TXEN, TXER valid
TXCLK pulse width high
TXCLK pulse width low
RXCLK (Input)
Characteristic
Characteristic
RXD[n:0]
Figure 23. MII Receive Signal Timing Diagram
RXDV,
RXER
Preliminary—Subject to Change Without Notice
Table 22. Transmit Signal Timing
Table 21. Receive Signal Timing
MCF5301x Data Sheet, Rev. 5
1
1
1
1
35%
35%
35%
35%
Min
Min
—
5
5
5
MII Mode
MII Mode
E1
E4
Valid Data
Max
65%
65%
Max
65%
65%
—
—
—
25
E3
E2
35%
35%
35%
35%
Min
Min
—
4
2
5
RMII Mode
RMII Mode
Preliminary Electrical Characteristics
Max
65%
65%
Max
65%
65%
10
—
—
—
RXCLK period
RXCLK period
t
t
TXCLK
TXCLK
Unit
Unit
ns
ns
ns
ns
37