MCF53014CMJ240J Freescale Semiconductor, MCF53014CMJ240J Datasheet - Page 40

• Manufacturer Part Number: MCF53014CMJ240J
• Description: IC MCU 32BIT 128KB 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF5301xr

Specifications of MCF53014CMJ240J

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB, USB OTG
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: Cache
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Processor Series: MCF5301x
• Core: ColdFire V3
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: I2C, UART, DSPI
• Maximum Clock Frequency: 400 KHz, 20 MHz, 25 MHz
• Number Of Timers: 4
• Operating Supply Voltage: - 0.5 V to + 2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: M53015EVB, M53017KIT, M53017MOD
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13 bit
• On-chip Dac: 16 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Preliminary Electrical Characteristics
40
1
2
3
4
5
Name
DS10
DS11
DS12
DS13
DS14
Timings shown are for DMCR[MTFE] = 0 (classic SPI) and DCTARn[CPHA] = 0. Data is sampled on the DSPI_SIN pin
on the odd-numbered DSPI_SCK edges and driven on the DSPI_SOUT pin on even-numbered DSPI edges.
When in master mode, the baud rate is programmable in DCTARn[DBR], DCTARn[PBR], and DCTARn[BR].
This specification assumes a 50/50 duty cycle setting. The duty cycle is programmable in DCTARn[DBR],
DCTARn[CPHA], and DCTARn[PBR].
The DSPI_PCSn to DSPI_SCK delay is programmable in DCTARn[PCSSCK] and DCTARn[CSSCK].
The DSPI_SCK to DSPI_PCSn delay is programmable in DCTARn[PASC] and DCTARn[ASC].
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
(DCTARn[CPOL] = 1)
(DCTARn[CPOL] = 0)
DSPI_SOUT
DSPI_PCSn
Table 26. DSPI Module AC Timing Specifications
DSPI_SCK
DSPI_SCK
DSPI_SIN
Characteristic
Figure 27. DSPI Classic SPI Timing — Master Mode
Preliminary—Subject to Change Without Notice
DS7
MCF5301x Data Sheet, Rev. 5
First Data
DS3
First Data
DS8
DS6
DS2
Symbol
DS2
—
—
—
—
—
Data
Data
Min
—
—
0
2
7
Last Data
DS1
Last Data
DS5
1
(continued)
DS4
Max
20
18
—
—
—
Freescale Semiconductor
Unit
ns
ns
ns
ns
ns
Notes