OM11049,598 NXP Semiconductors, OM11049,598 Datasheet
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LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller flash and 8 kB SRAM Rev. 4 — 10 February 2011 1. General description The LPC1111/12/13/14 are a ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for 8/16-bit microcontroller applications, offering ...
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... NXP Semiconductors Analog peripherals: 10-bit ADC with input multiplexing among 8 pins. Serial interfaces: UART with fractional baud rate generation, internal FIFO, and RS-485 support. Two SPI controllers with SSP features and with FIFO and multi-protocol capabilities (second SPI on LQFP48 and PLCC44 packages only). ...
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... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Name LPC1111FHN33/101 HVQFN33 LPC1111FHN33/102 HVQFN33 LPC1111FHN33/201 HVQFN33 LPC1111FHN33/202 HVQFN33 LPC1112FHN33/101 HVQFN33 LPC1112FHN33/102 HVQFN33 LPC1112FHN33/201 HVQFN33 LPC1112FHN33/202 HVQFN33 LPC1113FHN33/201 HVQFN33 LPC1113FHN33/202 HVQFN33 LPC1113FHN33/301 HVQFN33 LPC1113FHN33/302 HVQFN33 LPC1114FHN33/201 HVQFN33 LPC1114FHN33/202 HVQFN33 LPC1114FHN33/301 HVQFN33 ...
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... NXP Semiconductors 4.1 Ordering options Table 2. Ordering options Type number Series LPC1111 LPC1111FHN33/101 LPC1100 LPC1111FHN33/102 LPC1100L LPC1111FHN33/201 LPC1100 LPC1111FHN33/202 LPC1100L LPC1112 LPC1112FHN33/101 LPC1100 LPC1112FHN33/102 LPC1100L LPC1112FHN33/201 LPC1100 LPC1112FHN33/202 LPC1100L LPC1113 LPC1113FHN33/201 LPC1100 LPC1113FHN33/202 LPC1100L LPC1113FHN33/301 LPC1100 LPC1113FHN33/302 LPC1100L LPC1113FBD48/301 LPC1100 LPC1113FBD48/302 ...
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... NXP Semiconductors 5. Block diagram LPC1111/12/13/14 HIGH-SPEED GPIO ports GPIO PIO0/1/2/3 RXD TXD (1) DTR, DSR , CTS, (1) (1) DCD , RI , RTS CT32B0_MAT[3:0] 32-bit COUNTER/TIMER 0 CT32B0_CAP0 CT32B1_MAT[3:0] 32-bit COUNTER/TIMER 1 CT32B1_CAP0 CT16B0_MAT[2:0] 16-bit COUNTER/TIMER 0 CT16B0_CAP0 CT16B1_MAT[1:0] 16-bit COUNTER/TIMER 1 CT16B1_CAP0 (1) LQFP48 and PLCC44 packages only. Fig 1. LPC1111/12/13/14 block diagram ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning PIO2_6 PIO2_0/DTR/SSEL1 RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2 V XTALIN XTALOUT V PIO1_8/CT16B1_CAP0 PIO0_2/SSEL0/CT16B0_CAP0 PIO2_7 PIO2_8 Fig 2. Pin configuration LQFP48 package LPC1111_12_13_14 Product data sheet LPC1113FBD48/301 6 LPC1113FBD48/302 LPC1114FBD48/301 7 LPC1114FBD48/302 All information provided in this document is subject to legal disclaimers. Rev. 4 — 10 February 2011 ...
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... NXP Semiconductors RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2 XTALIN XTALOUT V PIO1_8/CT16B1_CAP0 PIO0_2/SSEL0/CT16B0_CAP0 PIO2_7 PIO2_8 PIO2_1/DSR/SCK1 Fig 3. Pin configuration PLCC44 package LPC1111_12_13_14 Product data sheet LPC1114FA44/301 12 DD LPC1114FA44/302 All information provided in this document is subject to legal disclaimers. Rev. 4 — 10 February 2011 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller 39 R/PIO1_2/AD3/CT32B1_MAT1 ...
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... NXP Semiconductors PIO2_0/DTR RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2 PIO1_8/CT16B1_CAP0 PIO0_2/SSEL0/CT16B0_CAP0 Fig 4. Pin configuration HVQFN 33 package LPC1111_12_13_14 Product data sheet terminal 1 index area XTALIN XTALOUT Transparent top view All information provided in this document is subject to legal disclaimers. Rev. 4 — 10 February 2011 LPC1111/12/13/14 32-bit ARM Cortex-M0 microcontroller ...
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... NXP Semiconductors 6.2 Pin description Table 3. LPC1113/14 pin description table (LQFP48 package) Symbol Pin Start logic input PIO0_0 to PIO0_11 [2] RESET/PIO0_0 3 yes [3] PIO0_1/CLKOUT/ 4 yes CT32B0_MAT2 [3] PIO0_2/SSEL0/ 10 yes CT16B0_CAP0 [3] PIO0_3 14 yes [4] PIO0_4/SCL 15 yes [4] PIO0_5/SDA 16 yes [3] PIO0_6/SCK0 22 yes [3] PIO0_7/CTS 23 yes [3] PIO0_8/MISO0/ 27 yes CT16B0_MAT0 [3] PIO0_9/MOSI0/ ...
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... NXP Semiconductors Table 3. LPC1113/14 pin description table (LQFP48 package) Symbol Pin Start logic input [3] SWCLK/PIO0_10/ 29 yes SCK0/ CT16B0_MAT2 [5] R/PIO0_11/ 32 yes AD0/CT32B0_MAT3 PIO1_0 to PIO1_11 [5] R/PIO1_0/ 33 yes AD1/CT32B1_CAP0 [5] R/PIO1_1 AD2/CT32B1_MAT0 [5] R/PIO1_2 AD3/CT32B1_MAT1 [5] SWDIO/PIO1_3 AD4/CT32B1_MAT2 [5] PIO1_4/AD5 CT32B1_MAT3/ WAKEUP LPC1111_12_13_14 Product data sheet …continued Type ...
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... NXP Semiconductors Table 3. LPC1113/14 pin description table (LQFP48 package) Symbol Pin Start logic input [3] PIO1_5/RTS CT32B0_CAP0 [3] PIO1_6/RXD CT32B0_MAT0 [3] PIO1_7/TXD CT32B0_MAT1 [3] PIO1_8 CT16B1_CAP0 [3] PIO1_9 CT16B1_MAT0 [5] PIO1_10/AD6 CT16B1_MAT1 [5] PIO1_11/AD7 42 no PIO2_0 to PIO2_11 [3] PIO2_0/DTR/SSEL1 2 no [3] PIO2_1/DSR/SCK1 13 no [3] PIO2_2/DCD/MISO1 26 no [3] PIO2_3/RI/MOSI1 38 no [3] PIO2_4 19 no [3] PIO2_5 ...
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... NXP Semiconductors Table 3. LPC1113/14 pin description table (LQFP48 package) Symbol Pin Start logic input [3] PIO2_10 25 no [3] PIO2_11/SCK0 31 no PIO3_0 to PIO3_5 [3] PIO3_0/DTR 36 no [3] PIO3_1/DSR 37 no [3] PIO3_2/DCD 43 no [3] PIO3_3/ [3] PIO3_4 18 no [3] PIO3_5 [6] XTALIN 6 - [6] XTALOUT [1] Pin state at reset for default function Input Output internal pull-up enabled inactive, no pull-up/down enabled. ...
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... NXP Semiconductors Table 4. LPC1114 pin description table (PLCC44 package) Symbol Pin Start logic input PIO0_0 to PIO0_11 [2] RESET/PIO0_0 7 yes [3] PIO0_1/CLKOUT/ 8 yes CT32B0_MAT2 [3] PIO0_2/SSEL0/ 14 yes CT16B0_CAP0 [3] PIO0_3 18 yes [4] PIO0_4/SCL 19 yes [4] PIO0_5/SDA 20 yes [3] PIO0_6/SCK0 26 yes [3] PIO0_7/CTS 27 yes [3] PIO0_8/MISO0/ 31 yes CT16B0_MAT0 [3] PIO0_9/MOSI0/ 32 yes CT16B0_MAT1 [3] SWCLK/PIO0_10/ ...
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... NXP Semiconductors Table 4. LPC1114 pin description table (PLCC44 package) Symbol Pin Start logic input [5] R/PIO0_11/ 36 yes AD0/CT32B0_MAT3 PIO1_0 to PIO1_11 [5] R/PIO1_0/ 37 yes AD1/CT32B1_CAP0 [5] R/PIO1_1 AD2/CT32B1_MAT0 [5] R/PIO1_2 AD3/CT32B1_MAT1 [5] SWDIO/PIO1_3/AD4 CT32B1_MAT2 [5] PIO1_4/AD5 CT32B1_MAT3/ WAKEUP [3] PIO1_5/RTS CT32B0_CAP0 [3] PIO1_6/RXD CT32B0_MAT0 LPC1111_12_13_14 Product data sheet …continued Type Reset ...
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... NXP Semiconductors Table 4. LPC1114 pin description table (PLCC44 package) Symbol Pin Start logic input [3] PIO1_7/TXD CT32B0_MAT1 [3] PIO1_8/CT16B1_CAP0 13 no [3] PIO1_9/CT16B1_MAT0 21 no [5] PIO1_10/AD6 CT16B1_MAT1 [5] PIO1_11/AD7 44 no PIO2_0 to PIO2_11 [3] PIO2_0/DTR/SSEL1 6 no [3] PIO2_1/DSR/SCK1 17 no [3] PIO2_2/DCD/MISO1 30 no [3] PIO2_3/RI/MOSI1 40 no [3] PIO2_4 23 no [3] PIO2_5 24 no [3] PIO2_6 5 no [3] PIO2_7 ...
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... NXP Semiconductors Table 4. LPC1114 pin description table (PLCC44 package) Symbol Pin Start logic input [3] PIO3_5 [6] XTALIN 10 - [6] XTALOUT [1] Pin state at reset for default function Input Output internal pull-up enabled inactive, no pull-up/down enabled. [2] See Figure 33 for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode ...
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... NXP Semiconductors Table 5. LPC1111/12/13/14 pin description table (HVQFN33 package) Symbol Pin Start logic input [4] PIO0_5/SDA 11 yes [3] PIO0_6/SCK0 15 yes [3] PIO0_7/CTS 16 yes [3] PIO0_8/MISO0/ 17 yes CT16B0_MAT0 [3] PIO0_9/MOSI0/ 18 yes CT16B0_MAT1 [3] SWCLK/PIO0_10/ 19 yes SCK0/ CT16B0_MAT2 [5] R/PIO0_11/AD0/ 21 yes CT32B0_MAT3 PIO1_0 to PIO1_11 [5] R/PIO1_0/AD1/ 22 yes CT32B1_CAP0 [5] R/PIO1_1/AD2 CT32B1_MAT0 [5] R/PIO1_2/AD3/ ...
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... NXP Semiconductors Table 5. LPC1111/12/13/14 pin description table (HVQFN33 package) Symbol Pin Start logic input [5] SWDIO/PIO1_3 AD4/CT32B1_MAT2 [5] PIO1_4/AD5 CT32B1_MAT3/ WAKEUP [3] PIO1_5/RTS CT32B0_CAP0 [3] PIO1_6/RXD CT32B0_MAT0 [3] PIO1_7/TXD CT32B0_MAT1 [3] PIO1_8 CT16B1_CAP0 [3] PIO1_9 CT16B1_MAT0 [5] PIO1_10/AD6 CT16B1_MAT1 [5] PIO1_11/AD7 27 no PIO2_0 [3] PIO2_0/DTR 1 no PIO3_0 to PIO3_5 [3] PIO3_2 28 no [3] PIO3_4 ...
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... NXP Semiconductors Table 5. LPC1111/12/13/14 pin description table (HVQFN33 package) Symbol Pin Start logic input [3] PIO3_5 [6] XTALIN 4 - [6] XTALOUT [1] Pin state at reset for default function Input Output internal pull-up enabled inactive, no pull-up/down enabled. [2] See Figure 33 for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode ...
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... NXP Semiconductors 7. Functional description 7.1 ARM Cortex-M0 processor The ARM Cortex- general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. 7.2 On-chip flash program memory The LPC1111/12/13/14 contain 32 kB (LPC1114 (LPC1113 (LPC1112 (LPC1111) of on-chip flash memory. 7.3 On-chip SRAM The LPC1111/12/13/14 contain a total of 8 kB on-chip static RAM memory ...
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... NXP Semiconductors LPC1111/12/13/ reserved private peripheral bus reserved AHB peripherals reserved APB peripherals 1 GB reserved 0.5 GB reserved 16 kB boot ROM reserved 8 kB SRAM (LPC1113/14/301/302 SRAM (LPC1111/12/13/14/201/202 SRAM (LPC1111/12/101/102) reserved 32 kB on-chip flash (LPC1114 on-chip flash (LPC1113 on-chip flash (LPC1112 on-chip flash (LPC1111 (1) LQFP48/PLCC44 packages only ...
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... NXP Semiconductors • In the LPC1111/12/13/14, the NVIC supports 32 vectored interrupts including inputs to the start logic from individual GPIO pins. • Four programmable interrupt priority levels with hardware priority level masking. • Software interrupt generation. 7.5.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags ...
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... NXP Semiconductors Support for RS-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode. The UART includes a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. 7.8.1 Features • ...
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... NXP Semiconductors receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I controlled by more than one bus master connected to it. 7.10.1 Features • The C-bus interface also supports Fast-mode Plus with bit rates Mbit/s. ...
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... NXP Semiconductors • Counter or timer operation. • One capture channel per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also generate an interrupt. • Four match registers per timer that allow: – Continuous operation with optional interrupt generation on match. ...
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... NXP Semiconductors 7.15 Clocking and power control 7.15.1 Crystal oscillators The LPC1111/12/13/14 include three independent oscillators. These are the system oscillator, the Internal RC oscillator (IRC), and the Watchdog oscillator. Each oscillator can be used for more than one purpose as required in a particular application. ...
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... NXP Semiconductors Upon power-up or any chip reset, the LPC1111/12/13/14 use the IRC as the clock source. Software may later switch to one of the other available clock sources. 7.15.1.2 System oscillator The system oscillator can be used as the clock source for the CPU, with or without using the PLL ...
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... NXP Semiconductors peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Selected peripherals have their own clock divider which provides even better power control. 7.15.5.1 Power profiles (LPC1100L series, LPC111x/102/202/302 only) The power consumption in Active and Sleep modes can be optimized for the application through simple calls to the power profile ...
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... NXP Semiconductors 7.16 System control 7.16.1 Start logic The start logic connects external pins to corresponding interrupts in the NVIC. Each pin shown in NVIC interrupt vector table. The start logic pins can serve as external interrupt pins when the chip is running. In addition, an input signal on the start logic pins can wake up the chip from Deep-sleep mode when all clocks are shut down ...
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... NXP Semiconductors 2. CRP2 disables access to the chip via the SWD and only allows full flash erase and update using a reduced set of the ISP commands. 3. Running an application with level CRP3 selected fully disables any access to the chip via the SWD pins and the ISP. This mode effectively disables ISP override using PIO0_1 pin, too the user’ ...
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... NXP Semiconductors 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (core and external rail input voltage I I supply current DD I ground current SS I I/O latch-up current latch T storage temperature stg T maximum junction temperature ...
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... NXP Semiconductors 9. Static characteristics Table 7. Static characteristics = −40 °C to +85 °C, unless otherwise specified. T amb Symbol Parameter V supply voltage (core DD and external rail) LPC1100 series (LPC111x/101/201/301) power consumption I supply current DD LPC1100L series (LPC111x/102/202/302) power consumption in low-current mode I supply current DD Standard port pins, RESET ...
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... NXP Semiconductors Table 7. Static characteristics = −40 °C to +85 °C, unless otherwise specified. T amb Symbol Parameter V input voltage I V output voltage O V HIGH-level input IH voltage V LOW-level input voltage IL V hysteresis voltage hys V HIGH-level output OH voltage V LOW-level output OL voltage I HIGH-level output OH current I LOW-level output ...
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... NXP Semiconductors Table 7. Static characteristics = −40 °C to +85 °C, unless otherwise specified. T amb Symbol Parameter V LOW-level input voltage IL V hysteresis voltage hys V HIGH-level output OH voltage V LOW-level output OL voltage I HIGH-level output OH current I LOW-level output OL current I LOW-level short-circuit OLS output current I pull-down current ...
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... NXP Semiconductors Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages. [ °C. [2] T amb [3] I measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled. DD [4] IRC enabled; system oscillator disabled; system PLL disabled. ...
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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. Fig 7. ADC characteristics LPC1111_12_13_14 Product data sheet ...
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... NXP Semiconductors 9.1 BOD static characteristics Table °C. T amb Symbol V th [1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC111x user manual. 9.2 Power consumption LPC111x/101/201/301 Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see LPC111x user manual): • ...
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... NXP Semiconductors (mA) (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 8. (mA) (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 9. LPC1111_12_13_14 Product data sheet ...
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... NXP Semiconductors (mA) (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 10. Sleep mode: Typical supply current I (μA) Fig 11. Deep-sleep mode: Typical supply current I LPC1111_12_13_14 Product data sheet −40 −15 Conditions 3.3 V; sleep mode entered from flash; all peripherals disabled in the DD SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F) ...
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... NXP Semiconductors (μA) Fig 12. Deep power-down mode: Typical supply current I 9.3 Power consumption LPC111x/102/202/302 Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see LPC111x user manual): • Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block. ...
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... NXP Semiconductors (mA) (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 13. Active mode: Typical supply current I (mA) (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. ...
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... NXP Semiconductors (mA) (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 15. Sleep mode: Typical supply current I LPC1111_12_13_14 Product data sheet −40 −15 Conditions 3.3 V; sleep mode entered from flash; all peripherals disabled in the DD SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F) ...
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... NXP Semiconductors (μA) Fig 16. Deep-sleep mode: Typical supply current I (μA) Fig 17. Deep power-down mode: Typical supply current I LPC1111_12_13_14 Product data sheet 5 4.5 3 3 2.5 1.5 −40 −15 Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register (PDSLEEPCFG = 0x0000 18FF). ...
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... NXP Semiconductors 9.4 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code is executed. Measured on a typical sample at T noted otherwise, the system oscillator and PLL are running in both measurements ...
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... NXP Semiconductors 9.5 Electrical pin characteristics V Fig 18. High-drive output: Typical HIGH-level output voltage V (mA) Fig 19. I LPC1111_12_13_14 Product data sheet 3 °C (V) 25 °C −40 °C 3.2 2.8 2 Conditions 3 pin PIO0_7. DD output current 0.2 Conditions 3 pins PIO0_4 and PIO0_5 C-bus pins (high current sink): Typical LOW-level output current I ...
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... NXP Semiconductors (mA) Fig 20. Typical LOW-level output current I V Fig 21. Typical HIGH-level output voltage V LPC1111_12_13_14 Product data sheet 0.2 Conditions 3.3 V; standard port pins and PIO0_7. DD 3 °C 25 °C 3.2 −40 °C 2.8 2 Conditions 3.3 V; standard port pins All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors (μA) Fig 22. Typical pull-up current I (μA) Fig 23. Typical pull-down current I LPC1111_12_13_14 Product data sheet −10 − °C 25 °C −40 °C −50 − Conditions 3.3 V; standard port pins. DD versus input voltage ° °C −40 ° Conditions 3.3 V; standard port pins. ...
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... NXP Semiconductors 10. Dynamic characteristics 10.1 Power-up ramp conditions Table 11. = −40 °C to +85 °C. T amb Symbol Parameter wait V I [1] See [2] The wait time specifies the time the power supply must be at levels below 400 mV before ramping up. Fig 24. Power-up ramp 10.2 Flash memory Table 12. = − ...
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... NXP Semiconductors 10.3 External clock Table 13. = −40 °C to +85 ° amb Symbol f osc T cy(clk) t CHCX t CLCX t CLCH t CHCL [1] Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply [2] voltages ...
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... NXP Semiconductors 10.4 Internal oscillators Table 14. = −40 °C to +85 °C; 2.7 V ≤ amb Symbol f osc(RC) [1] Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply [2] voltages. (MHz) Fig 26 ...
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... NXP Semiconductors 10.5 I/O pins Table 16. = −40 °C to +85 °C; 3.0 V ≤ amb Symbol [1] Applies to standard port pins and RESET pin. 2 10.6 I C-bus Table 17. = −40 °C to +85 °C. T amb Symbol f SCL LOW t HIGH t HD;DAT t SU;DAT [1] See the I [2] Parameters are valid over operating temperature range unless otherwise specified. ...
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... NXP Semiconductors [6] The maximum t output stage t SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified t [7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing. ...
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... NXP Semiconductors Table 18. Dynamic characteristics of SPI pins in SPI mode Symbol Parameter T PCLK cycle time cy(PCLK) t data set-up time DS t data hold time DH t data output valid time in SPI mode v(Q) t data output hold time in SPI mode h(Q) = (SSPCLKDIV × SCR) × CPSDVSR ...
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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 29. SPI slave timing in SPI mode LPC1111_12_13_14 Product data sheet T cy(clk) MOSI DATA VALID t MISO DATA VALID MOSI DATA VALID t v(Q) MISO DATA VALID Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1. ...
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... NXP Semiconductors 11. Application information 11.1 ADC usage notes The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in • The ADC input trace must be short and as close as possible to the LPC1111/12/13/14 chip. • The ADC input traces must be shielded from fast switching digital signals and noisy power supply lines. • ...
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... NXP Semiconductors Fig 31. Oscillator modes and models: oscillation mode of operation and external crystal Table 19. Fundamental oscillation frequency F 1 MHz - 5 MHz 5 MHz - 10 MHz 10 MHz - 15 MHz 15 MHz - 20 MHz Table 20. Fundamental oscillation frequency F 15 MHz - 20 MHz 20 MHz - 25 MHz 11.3 XTAL Printed Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip ...
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... NXP Semiconductors order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of C accordingly to the increase in parasitics of the PCB layout. 11.4 Standard I/O pad configuration Figure 32 • Digital output driver • Digital input: Pull-up enabled/disabled • ...
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... NXP Semiconductors 11.5 Reset pad configuration Fig 33. Reset pad configuration 11.6 ElectroMagnetic Compatibility (EMC) Radiated emission measurements according to the IEC61967-2 standard using the TEM-cell method are shown for the LPC1114FBD48/302 in Table 21 3 Parameter Input clock: IRC (12 MHz) maximum peak level IEC level ...
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... NXP Semiconductors 12. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 1.6 mm 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...
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... NXP Semiconductors PLCC44: plastic leaded chip carrier; 44 leads pin 1 index 6 β DIMENSIONS (mm dimensions are derived from the original inch dimensions UNIT max. min. 4.57 0.53 mm 0.51 0.25 3.05 4.19 0.33 0.180 0.021 inches 0.02 0.01 0.12 0.165 0.013 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 0.85 mm terminal 1 index area terminal 1 32 index area Dimensions (1) Unit max 1.00 0.05 0.35 mm nom 0.85 0.02 0.28 0.2 min 0.80 0.00 0.23 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 13. Abbreviations Table 22. Acronym ADC AHB APB BOD GPIO PLL RC SPI SSI SSP TEM UART LPC1111_12_13_14 Product data sheet Abbreviations Description Analog-to-Digital Converter Advanced High-performance Bus Advanced Peripheral Bus BrownOut Detection General Purpose Input/Output Phase-Locked Loop Resistor-Capacitor Serial Peripheral Interface ...
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... NXP Semiconductors 14. Revision history Table 23. Revision history Document ID Release date LPC1111_12_13_14 v.4 20110210 Modifications: LPC1111_12_13_14 v.3 20101110 Modifications: LPC1111_12_13_14 v.2 20100818 Modifications: LPC1111_12_13_14 v.1 20100416 LPC1111_12_13_14 Product data sheet Data sheet status Product data sheet • Power consumption graphs added for parts LPC111x/102/202/302 Figure 17) ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... For sales office addresses, please send an email to: LPC1111_12_13_14 Product data sheet own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 Functional description . . . . . . . . . . . . . . . . . . 20 7.1 ARM Cortex-M0 processor . . . . . . . . . . . . . . . 20 7.2 On-chip flash program memory . . . . . . . . . . . 20 7.3 On-chip SRAM ...