A2F500M3G-FGG256 Actel, A2F500M3G-FGG256 Datasheet
A2F500M3G-FGG256
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A2F500M3G-FGG256 Summary of contents
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SmartFusion Intelligent Mixed Signal FPGAs Microcontroller Subsystem (MSS) ® • Hard 100 MHz 32-Bit ARM Cortex™-M3 – 1.25 DMIPS/MHz Throughput from Zero Wait State Memory – Memory Protection Unit (MPU) – Single Cycle Multiplication, Hardware Divide – JTAG Debug (4 ...
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SmartFusion Intelligent Mixed Signal FPGAs SmartFusion Family Product Table SmartFusion Device FPGA Fabric System Gates Tiles (D-flip-flops) RAM Blocks (4,608 bits) Microcontroller Flash (Kbytes) Subsystem (MSS) SRAM (Kbytes) Cortex-M3 with memory protection unit (MPU) 10/100 Ethernet MAC External Memory Controller ...
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Package I/Os: MSS + FPGA I/Os Device A2F060 Package CS288 Direct Analog Inputs 6 1 Shared Analog Inputs 4 Total Analog Inputs 10 Total Analog Outputs 1 2,3 4 MSS I/Os 28 FPGA I/Os 68 Total I/Os 107 Notes: 1. ...
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SmartFusion Intelligent Mixed Signal FPGAs SmartFusion Block Diagram Supervisor PLL OSC RC + WDT 32 KHz RTC – APB SPI 1 UART 1 EFROM PDMA IAP SCB Volt Mon. Temp. (ABPS) Mon. ...
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SmartFusion System Architecture ISP AES Decryption Cortex-M3 Microcontroller Subsystem (MSS) SCB Note: Architecture for A2F500 Bank 0 Embedded FlashROM (eFROM) SCB ADC and DAC ADC and DAC Bank 3 Osc. CCC MSS FPGA PLL/CCC Revision 6 SmartFusion Intelligent Mixed Signal ...
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SmartFusion Intelligent Mixed Signal FPGAs Product Ordering Codes _ A2F200 eNVM Size Kbytes Kbytes Kbytes Kbytes E = 128 Kbytes F = 256 Kbytes G ...
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Table of Contents SmartFusion Device Family Overview Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents Datasheet Information List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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SmartFusion Device Family Overview Introduction The SmartFusion family of intelligent mixed signal FPGAs builds on the technology first introduced with the Fusion mixed signal FPGAs. SmartFusion devices are made possible by integrating FPGA technology with programmable high-performance analog ...
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SmartFusion Device Family Overview ProASIC3 FPGA Fabric The SmartFusion family, based on the proven, low power, firm-error immune ProASIC architecture, benefits from the advantages only flash-based devices offer: Reduced Cost of Ownership Advantages to the designer extend beyond low unit ...
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PCB design. Flash-based SmartFusion devices simplify total system design and reduce cost and design risk, while increasing system reliability. Immunity to Firm Errors Firm errors occur most commonly when high-energy neutrons, generated in the atmosphere, ...
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SmartFusion DC and Switching Characteristics General Specifications Operating Conditions Stresses beyond the operating conditions listed in device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings are stress ratings only; functional ...
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SmartFusion DC and Switching Characteristics Table 2-2 • Analog Maximum Ratings Parameter ABPS[n] pad voltage (relative to ground) GDEC[1: (±15.36 V range) CM[n] pad voltage relative to ground) TM[n] pad voltage (relative to ground) ADC[n] pad voltage (relative ...
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Table 2-3 • Recommended Operating Conditions Symbol T Junction temperature J 2 VCC 1 core supply voltage VJTAG JTAG DC voltage VPP Programming voltage VCCPLLx Analog power supply (PLL) VCCFPGAIOBx/ 1 supply voltage 4 VCCMSSIOBx 1.8 ...
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SmartFusion DC and Switching Characteristics Table 2-4 • FPGA and Embedded Flash Programming, Storage and Operating Limits Product Grade Storage Temperature Commercial Min 0°C J Min 85°C J Industrial Min –40°C J Min. T ...
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Chip is in the SoC Mode. VCCxxxxIOBx Trip Point: Ramping up: 0.6 V < trip_point_up < 1.2 V Ramping down: 0.5 V < trip_point_down < 1.1 V VCC Trip Point: Ramping up: 0.6 V < trip_point_up < 1.1 V ...
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SmartFusion DC and Switching Characteristics VCC = VCCxxxxIOBx + VT where VT can be from 0. 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 1: I/O Buffers are OFF VCC = 1.425 V Region 2: ...
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Thermal Characteristics Introduction The temperature variable in the SoC Products Group Designer software refers to the junction temperature, not the ambient, case, or board temperatures. This is an important distinction because dynamic and static power consumption will cause the chip's ...
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SmartFusion DC and Switching Characteristics Theta-JA Junction-to-ambient thermal resistance (θ JEDEC (JESD-51), but it has little relevance in actual performance of the product. It should be used with caution but is useful for comparing the thermal performance of one package ...
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------------------ - The 1.76 W power is less than the required 3.00 W. The design therefore requires a heat sink, or the airflow where the device is mounted should be increased. The design's total junction-to-air thermal resistance ...
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SmartFusion DC and Switching Characteristics Calculating Power Dissipation Quiescent Supply Current Table 2-8 • Quiescent Supply Current Characteristics Modes and Power Supplies Time Keeping mode Standby mode On* 3.3 V Parameter Modes IDC1 Time Keeping mode ...
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Table 2-10 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings Applicable to MSS I/O Banks Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS / 3.3 V LVCMOS – Schmitt trigger 2.5 ...
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SmartFusion DC and Switching Characteristics Power Consumption of Various Internal Resources Table 2-13 • Different Components Contributing to Dynamic Power Consumption in SmartFusion Devices Parameter Definition PAC1 Clock contribution of a Global Rib PAC2 Clock contribution of a Global Spine ...
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Table 2-13 • Different Components Contributing to Dynamic Power Consumption in SmartFusion Devices Parameter Definition PAC25 ABPS Power Contribution PAC26 Sigma-Delta DAC Power Contribution PAC27 Comparator Power Contribution PAC28 Voltage Regulator Power Contribution Notes: 1. For a different use of ...
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SmartFusion DC and Switching Characteristics Power Calculation Methodology This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in the Libero IDE software. The power calculation ...
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Standby Mode DYN RC-OSC LPXTAL-OSC Time Keeping Mode DYN LPXTAL-OSC Global Clock Dynamic Contribution—P SoC Mode CLOCK AC1 SPINE AC2 N is the ...
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SmartFusion DC and Switching Characteristics Standby Mode and Time Keeping Mode NET I/O Input Buffer Dynamic Contribution—P SoC Mode INPUTS INPUTS Where the number of I/O input buffers used ...
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Standby Mode and Time Keeping Mode PLL Embedded Nonvolatile Memory Dynamic Contribution—P SoC Mode The eNVM dynamic power consumption is a piecewise linear function of frequency. β eNVM eNVM-BLOCKS 4 ...
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SmartFusion DC and Switching Characteristics Microcontroller Subsystem Dynamic Contribution—P SoC Mode MSS AC22 Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic element relative to a clock percentage. ...
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User I/O Characteristics Timing Model I/O Module (Registered 1. LVPECL D Q (Applicable to FPGA I/O Bank, EMC pin 0.24 ns ICLKQ t = 0.27 ns ISUD Input LVTTL Clock Register Cell t = ...
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SmartFusion DC and Switching Characteristics t PY PAD t = MAX MAX(t DIN V trip PAD 50% Y GND t PY (R) DIN GND Figure 2-3 • Input Buffer Timing Model and Delays (example ...
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DOUT D Q CLK D From Array I/O Interface D DOUT PAD Figure 2-4 • Output Buffer Model and Delays (example) SmartFusion Intelligent Mixed Signal FPGAs t DP DOUT t = MAX(t (R MAX(t ...
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SmartFusion DC and Switching Characteristics t EOUT D Q CLK CLK D I/O Interface D 50 EOUT (R) 50% EOUT t ZL PAD V trip VOL D 50 EOUT (R) VCC 50% EOUT ...
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Overview of I/O Performance Summary of I/O DC Input and Output Levels – Default I/O Software Settings Table 2-18 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial Conditions—Software Default Settings Applicable to FPGA I/O ...
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SmartFusion DC and Switching Characteristics Table 2-20 • Summary of Maximum and Minimum DC Input Levels Applicable to Commercial Conditions in all I/O Bank Types DC I/O Standards 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V ...
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Table 2-23 • Summary of I/O Timing Characteristics—Software Default Settings –1 Speed Grade, Worst Commercial-Case Conditions: T Worst-Case VCCxxxxIOBx (per standard) Applicable to FPGA I/O Banks, Assigned to EMC I/O Pins I/O Standard 3.3 V LVTTL / 12 mA High ...
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... CCImax 2- 26 Definition Conditions 1.0 MHz 1.0 MHz IN 1 Drive Strength Per PCI/PCI-X specification http://www.actel.com/download/ibis/default.aspx ) / I OLspec OLspec – OHspec OHspe visio n 6 Min. Max. Units PULL-DOWN PULL- (Ω) (Ω) 100 300 100 300 50 150 50 150 100 200 100 ...
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... These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCxxxxIOBx, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the SoC Products Group website at http://www.actel.com/download/ibis/default.aspx ...
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SmartFusion DC and Switching Characteristics Table 2-29 • I/O Short Currents I Applicable to FPGA I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI/PCI-X Note 85°C. ...
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The length of time an I/O can withstand I reliability data below is based I/O setting, which is the worst case for this type of analysis. For example, at 100°C, the short current condition ...
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SmartFusion DC and Switching Characteristics Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor–Transistor Logic (LVTTL general-purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. Table 2-34 ...
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Timing Characteristics Table 2-37 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Worst Commercial-Case Conditions: T Worst-Case VCCxxxxIOBx = 3.0 V Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins Drive Speed Strength Grade t t ...
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SmartFusion DC and Switching Characteristics 2.5 V LVCMOS Low-Voltage CMOS for 2 extension of the LVCMOS standard (JESD8-5) used for general- purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer. Table ...
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Timing Characteristics Table 2-43 • 2.5 V LVCMOS High Slew Worst Commercial-Case Conditions: T Worst-Case VCCxxxxIOBx = 2.3 V Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins Drive Speed Strength Grade t t DOUT ...
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SmartFusion DC and Switching Characteristics 1.8 V LVCMOS Low-voltage CMOS for 1 extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer. ...
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Timing Characteristics Table 2-49 • 1.8 V LVCMOS High Slew Worst Commercial-Case Conditions: T Worst-Case VCCxxxxIOBx = 1.7 V Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins Drive Speed Strength Grade t t DOUT ...
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SmartFusion DC and Switching Characteristics Table 2-51 • 1.8 V LVCMOS High Slew Worst Commercial-Case Conditions: T Worst-Case VCCxxxxIOBx = 1.7 V Applicable to MSS I/O Banks Drive Speed Strength Grade t DOUT 4 mA Std. 0.22 –1 0.18 Notes: ...
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V LVCMOS (JESD8-11) Low-Voltage CMOS for 1 extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer. Table 2-52 • Minimum ...
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SmartFusion DC and Switching Characteristics Timing Characteristics Table 2-55 • 1.5 V LVCMOS High Slew Worst Commercial-Case Conditions: T Worst-Case VCCxxxxIOBx = 1.425 V Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins Drive Speed Strength Grade t ...
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V PCI, 3.3 V PCI-X Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus applications. Table 2-58 • Minimum and Maximum DC Input and Output Levels 3.3 V PCI/PCI-X VIL Min. ...
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SmartFusion DC and Switching Characteristics Differential I/O Characteristics Physical Implementation Configuration of the I/O modules as a differential pair is handled by SoC Products Group Designer software when the user instantiates a differential I/O macro in the design. Differential I/Os ...
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Table 2-62 • LVDS Minimum and Maximum DC Input and Output Levels DC Parameter Description VCCFPGAIOBx Supply voltage VOL Output low voltage VOH Output high voltage 1 I Output lower current Output high current OH VI Input ...
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SmartFusion DC and Switching Characteristics B-LVDS/M-LVDS Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers. SoC Products ...
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LVPECL Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination. The full implementation of the ...
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SmartFusion DC and Switching Characteristics I/O Register Specifications Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset Preset Data D C DFN1E1P1 E Enable B CLK A Data Input I/O Register with: Active High Enable Active High Preset Positive-Edge ...
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Table 2-68 • Parameter Definition and Measuring Nodes Parameter Name t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data Register OSUD t Data Hold Time for the Output Data Register OHD t Enable ...
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SmartFusion DC and Switching Characteristics Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear D Data CC E Enable BB CLK AA CLR DD Data Input I/O Register with Active High Enable Active High Clear Positive-Edge Triggered Figure 2-15 ...
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Table 2-69 • Parameter Definition and Measuring Nodes Parameter Name t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data Register OSUD t Data Hold Time for the Output Data Register OHD t Enable ...
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SmartFusion DC and Switching Characteristics Input Register 50% 50% CLK t ISUD 50% 1 Data Enable 50% t IHE t Preset ISUE Clear Out_1 Figure 2-16 • Input Register Timing Diagram Timing Characteristics Table 2-70 • Input Data Register Propagation ...
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Output Register 50% CLK 1 50% Data_out Enable 50% t OHE t Preset OSUE Clear DOUT Figure 2-17 • Output Register Timing Diagram Timing Characteristics Table 2-71 • Output Data Register Propagation Delays Worst Commercial-Case Conditions: T Parameter t Clock-to-Q ...
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SmartFusion DC and Switching Characteristics Output Enable Register 50% 50% CLK t OESUD 1 50% D_Enable 50% Enable t t OESUE OEHE Preset Clear EOUT Figure 2-18 • Output Enable Register Timing Diagram Timing Characteristics Table 2-72 • Output Enable ...
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DDR Module Specifications Input DDR Module INBUF A Data B CLK CLKBUF C CLR INBUF Figure 2-19 • Input DDR Timing Model Table 2-73 • Parameter Definitions Parameter Name Parameter Definition t Clock-to-Out Out_QR DDRICLKQ1 t Clock-to-Out Out_QF DDRICLKQ2 t ...
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SmartFusion DC and Switching Characteristics CLK Data 1 2 CLR t DDRIREMCLR t DDRICLR2Q1 Out_QF t DDRICLR2Q2 Out_QR Figure 2-20 • Input DDR Timing Diagram Timing Characteristics Table 2-74 • Input DDR Propagation Delays Worst Commercial-Case Conditions: T Parameter t ...
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Output DDR Module Data_F (from core) CLK CLKBUF Data_R (from core) CLR INBUF Figure 2-21 • Output DDR Timing Model Table 2-75 • Parameter Definitions Parameter Name Parameter Definition t Clock-to-Out DDROCLKQ t Asynchronous Clear-to-Out DDROCLR2Q t Clear Removal DDROREMCLR ...
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SmartFusion DC and Switching Characteristics CLK Data_F DDROREMCLR Data_R CLR DDROREMCLR t DDROCLR2Q Out Figure 2-22 • Output DDR Timing Diagram Timing Characteristics Table 2-76 • Output DDR Propagation Delays Worst Commercial-Case Conditions: T ...
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VersaTile Characteristics VersaTile Specifications as a Combinatorial Module The SmartFusion library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer to the ProASIC3/E, and SmartFusion ...
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SmartFusion DC and Switching Characteristics OUT GND VCC OUT Figure 2-24 • Timing Model and Waveforms NAND2 or Any Combinatorial Logic MAX PD(FF) applicable for the particular ...
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Timing Characteristics Table 2-77 • Combinatorial Cell Propagation Delays Worst Commercial-Case Conditions: T Combinatorial Cell Equation INV AND2 · B NAND2 Y = !(A · B) OR2 NOR2 Y ...
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SmartFusion DC and Switching Characteristics 50% 50% CLK t SUD 50% Data EN 50 PRE SUE CLR Out t CLKQ Figure 2-26 • Timing Model and Waveforms Timing Characteristics Table 2-78 • Register Delays Worst Commercial-Case Conditions: ...
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Global Resource Characteristics A2F200 Clock Tree Topology Clock delays are device-specific. global tree presented in Figure 2-27 is used to drive all D-flip-flops in the device. CCC Figure 2-27 • Example of Global Tree Use in an A2F200 Device for ...
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SmartFusion DC and Switching Characteristics Global Tree Timing Characteristics Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are I/O standard–dependent, and the ...
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RC Oscillator The table below describes the electrical characteristics of the RC oscillator. RC Oscillator Characteristics Table 2-81 • Electrical Characteristics of the RC Oscillator Parameter Description FRC Operating frequency Accuracy Output jitter Output duty cycle IDYNRC Operating current SmartFusion ...
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SmartFusion DC and Switching Characteristics Main and Lower Power Crystal Oscillator The tables below describes the electrical characteristics of the main and low power crystal oscillator. Table 2-82 • Electrical Characteristics of the Main Crystal Oscillator Parameter Description Operating frequency ...
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Clock Conditioning Circuits CCC Electrical Specifications Timing Characteristics Table 2-84 • SmartFusion CCC/PLL Specification Parameter Clock Conditioning Circuitry Input Frequency f Clock Conditioning Circuitry Output Frequency f Delay Increments in Programmable Delay Blocks Number of Programmable Values in Each Programmable ...
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SmartFusion DC and Switching Characteristics FPGA Fabric SRAM and FIFO Characteristics FPGA Fabric SRAM ADDRA11 ADDRA10 ADDRA0 DINA8 DINA7 DINA0 WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA ADDRB11 ADDRB10 ADDRB0 DINB8 DINB7 DINB0 WIDTHB1 WIDTHB0 PIPEB WMODEB BLKB WENB CLKB ...
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Timing Waveforms t CYC t CKH CLK ADD 0 t BKS BLK_B t ENS WEN_B Figure 2-30 • RAM Read for Pass-Through Output t CYC t CKH CLK ...
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SmartFusion DC and Switching Characteristics CLK ADD 0 t BKS BLK_B t ENS WEN_B Figure 2-32 • RAM Write, Output Retained (WMODE = 0) CLK t AS ADD t BKS BLK_B t ...
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CYC t CKH CLK RESET_B Figure 2-34 • RAM Reset SmartFusion Intelligent Mixed Signal FPGAs t CKL t RSTBQ ...
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SmartFusion DC and Switching Characteristics Timing Characteristics Table 2-85 • RAM4K9 Worst Commercial-Case Conditions: T Parameter t Address setup time AS t Address hold time AH t REN_B, WEN_B setup time ENS t REN_B, WEN_B hold time ENH t BLK_B ...
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Table 2-86 • RAM512X18 Worst Commercial-Case Conditions: T Parameter t Address setup time AS t Address hold time AH t REN_B, WEN_B setup time ENS t REN_B, WEN_B hold time ENH t Input data (DI) setup time DS t Input ...
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SmartFusion DC and Switching Characteristics FIFO Figure 2-35 • FIFO Model 2- 70 FIFO4K18 RW2 RD17 RW1 RD16 RW0 WW2 WW1 RD0 WW0 ESTOP FULL FSTOP AFULL EMPTY AEVAL11 AEMPTY AEVAL10 AEVAL0 AFVAL11 AFVAL10 AFVAL0 REN RBLK RCLK WD17 WD16 ...
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Timing Waveforms RCLK/ WCLK RESET_B t RSTFG EMPTY AEMPTY t RSTFG FULL AFULL WA/RA (Address Counter) Figure 2-36 • FIFO Reset RCLK EMPTY AEMPTY WA/RA NO MATCH (Address Counter) Figure 2-37 • FIFO EMPTY Flag and AEMPTY Flag Assertion SmartFusion ...
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SmartFusion DC and Switching Characteristics WCLK FULL AFULL WA/RA NO MATCH (Address Counter) Figure 2-38 • FIFO FULL Flag and AFULL Flag Assertion WCLK MATCH WA/RA NO MATCH (EMPTY) (Address Counter) 1st Rising Edge After 1st Write RCLK EMPTY AEMPTY ...
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Timing Characteristics Table 2-87 • FIFO Worst Commercial-Case Conditions: T Parameter t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t BLK_B Setup Time BKS t BLK_B Hold Time BKH t Input Data (DI) Setup Time DS ...
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SmartFusion DC and Switching Characteristics Embedded FlashROM (eFROM) Electrical Characteristics Table 2-89 describes the eFROM maximum performance Table 2-89 • FlashROM Access Time, Worse Commercial Case Conditions: T Parameter t Clock to out per configuration* CK2Q F Maximum Clock frequency ...
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Programmable Analog Specifications Current Monitor Unless otherwise noted, current monitor performance is specified at 25°C with nominal power supply voltages, with the output measured using the internal voltage reference with the internal ADC in 12-bit mode and 91 Ksps, after ...
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SmartFusion DC and Switching Characteristics Temperature Monitor Unless otherwise noted, temperature monitor performance is specified with a 2N3904 diode-connected bipolar transistor from National Semiconductor or Infineon Technologies, nominal power supply voltages, with the output measured using the internal voltage reference ...
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Figure 2-41 • Temperature Error Versus External Capacitance Analog-to-Digital Converter (ADC) Unless otherwise noted, ADC direct input performance is specified at 25°C with nominal power supply voltages, ...
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SmartFusion DC and Switching Characteristics Table 2-93 • ADC Specifications (continued) Specification Effective number of bits (ENOB) SINAD 1.76 dB – ENOB = -------------------------------------------- - 6.02 dB/bit EQ 10 Full power bandwidth Analog settling time Input capacitance Input resistance Input ...
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Analog Bipolar Prescaler (ABPS) With the ABPS set to its high range setting (GDEC = 00), a hypothetical input voltage in the range –15. +15. scaled and offset by the ABPS input amplifier to match the ...
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SmartFusion DC and Switching Characteristics Table 2-94 • ABPS Performance Specifications (continued) Specification Analog settling time Input resistance Power supply rejection ratio ABPS power supply current requirements (not including ADC or VAREFx Test Conditions To 0.1% of final ...
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Comparator Unless otherwise specified, performance is specified at 25°C with nominal power supply voltages. Table 2-95 • Comparator Performance Specifications Specification Input voltage range Input offset voltage Input bias current Input resistance Power supply rejection ratio Propagation delay Hysteresis (± ...
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SmartFusion DC and Switching Characteristics Analog Sigma-Delta Digital to Analog Converter (DAC) Unless otherwise noted, sigma-delta DAC performance is specified at 25°C with nominal power supply voltages, using the internal sigma-delta modulators with 16-bit inputs, HCLK = 100 MHz, modulator ...
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Figure 2-43 • Sigma-Delta DAC Setting Time SmartFusion Intelligent Mixed Signal FPGAs Sigma Delta DAC Settling Time ...
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SmartFusion DC and Switching Characteristics Voltage Regulator Table 2-97 • Voltage Regulator Symbol Parameter V Output voltage T = 25°C OUT J V Output offset voltage T = 25° ICC33A Operation current T = 25°C J ΔV Load ...
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Figure 2-44 • Typical Output Voltage -10 -40 -20 Figure 2-45 • Load Regulation SmartFusion Intelligent Mixed Signal ...
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... These values are provided for a load of 35 pF. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Microsemi SoC Products Group website: http://www.actel.com/download/ibis/default.aspx. 2. For allowable pclk configurations, refer to the Serial Peripheral Interface Controller section in the Microcontroller Subsystem User’ ...
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... These values are provided for a load of 35 pF. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Microsemi SoC Products Group website: http://www.actel.com/download/ibis/default.aspx. 2. For allowable pclk configurations, refer to the Serial Peripheral Interface Controller section in the Microcontroller Subsystem User’ ...
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... IBIS models located on the SoC Products Group website at http://www.actel.com/download/ibis/default.aspx. 2. These values are provided for a load of 100 pF and 400 pF. For board design considerations and detailed output buffer resistances, use the corresponding http://www.actel.com/download/ibis/default.aspx. 3. For allowable Pclk configurations, refer to the Inter-Integrated Circuit (I Microcontroller Subsystem User’s Guide Characteristics 2 C interface ...
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... IBIS models located on the SoC Products Group website at http://www.actel.com/download/ibis/default.aspx. 2. These values are provided for a load of 100 pF and 400 pF. For board design considerations and detailed output buffer resistances, use the corresponding http://www.actel.com/download/ibis/default.aspx. 3. For allowable Pclk configurations, refer to the Inter-Integrated Circuit (I Microcontroller Subsystem User’s Guide. SDA T RISE ...
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SmartFusion Development Tools SmartFusion applications will be developed by a multi-discipline team of designers working on one project or one designer acting in several roles. The Microsemi SoC Products Group has developed design tools and flows to meet ...
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... Cortex™ Microcontroller Software Interface Standard (CMSIS Figure 3-2. Customer Alogorithms/ Intellectual Property Third Party TCP, HTTP, SMTP DHCP, LCD Third Party µC/OSII Actel or Third Party For Hard IP or Soft SPI, UART, NVM RAM, 10/100, Timer Actel CMSIS-based Actel SmartFusion ...
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... Micrium's ease-of-use, ease-of-integration, short learning curve, unsurpassed documentation, and clean code. SmartFusion Intelligent Mixed Signal FPGAs SoftConsole Vision IDE www.actel.com www.keil.com 32 K code limited N/A Full version GNU GCC RealView C/C++ GDB debug Vision Debugger No ...
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SmartFusion Programming SmartFusion devices have three separate flash areas that can be programmed: 1. The FPGA fabric 2. The embedded nonvolatile memories (eNVMs) 3. The embedded flash ROM (eFROM) There are essentially three methodologies for programming these areas: ...
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SmartFusion Programming The JTAGSEL pin selects the FPGA TAP controller or the Cortex-M3 debug logic. When JTAG SEL is asserted, the FPGA TAP controller is selected and the TRSTB input into the Cortex-M3 is held in a reset state (logic ...
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... Fusion FGPA Fabric User’s Guide http://www.actel.com/documents/Fusion_UG.pdf Chapters: "In-System Programming (ISP) of Actel’s Low-Power Flash Devices Using FlashPro4/3/3X" "Security in Low Power Flash Devices" "Programming Flash Devices" "Microprocessor Programming of Actel’s Low-Power Flash Devices" SmartFusion Intelligent Mixed Signal FPGAs ...
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Pin Descriptions Supply Pins Name Type GND Ground Digital ground to the FPGA fabric, microcontroller subsystem and GPIOs GND15ADC0 Ground Quiet analog ground to the 1.5 V circuitry of the first analog-to-digital converter (ADC) GND15ADC1 Ground Quiet analog ...
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Pin Descriptions Name Type VCC15A Supply Clean analog 1.5 V supply to the analog circuitry VCC15ADC0 Supply Analog 1.5 V supply to the first ADC VCC15ADC1 Supply Analog 1.5 V supply to the second ADC VCC15ADC2 Supply Analog 1.5 V ...
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Name Type VCCMAINXTAL Supply Analog supply to the main crystal oscillator circuit VCCMSSIOB2 Supply Supply voltage to the microcontroller subsystem I/O bank 2 (east MSS I/O bank) for the output buffers and I/O logic VCCMSSIOB4 Supply Supply voltage to the ...
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Pin Descriptions User-Defined Supply Pins Polarity/Bus Name Type Size VAREF0 Input 1 VAREF1 Input 1 VAREF2 Input 1 VAREFOUT Out Description Analog reference voltage for first ADC The SmartFusion device can be configured to generate a ...
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User Pins Name Type Polarity/Bus Size GPIO_x In/out 32 IO In/out SmartFusion Intelligent Mixed Signal FPGAs Description Microcontroller Subsystem (MSS) General Purpose I/O (GPIO). The MSS GPIO pin functions as an input, output, tristate, or bidirectional buffer with configurable interrupt ...
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Pin Descriptions Special Function Pins Name Type Polarity/Bus Size NC DC LPXIN In 1 LPXOUT In 1 MAINXIN In 1 MAINXOUT Out 1 NCAP Description No connect This pin is not connected to circuitry within the ...
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Name Type Polarity/Bus Size PCAP 1 PTBASE 1 PTEM 1 MSS_RESET_N In Low PU_N In Low SmartFusion Intelligent Mixed Signal FPGAs Description Positive Capacitor connection. This is the positive terminal of the charge pump. A capacitor, with a 2.2 µF ...
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Pin Descriptions JTAG Pins SmartFusion devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1 3.3 V (nominal). VCC must also be powered for the JTAG state ...
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Table 5-1 • Recommended Tie-Off Values for the TCK and TRST Pins V JTAG V at 3.3 V JTAG V at 2.5 V JTAG V at 1.8 V JTAG V at 1.5 V JTAG Notes: 1. The TCK pin can ...
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Pin Descriptions Microcontroller Subsystem (MSS) Polarity/ Name Type Bus Size External Memory Controller EMC_ABx Out 26 EMC_BYTENx Out LOW/2 EMC_CLK Out Rise EMC_CSx_N Out LOW/2 EMC_DBx In/out 16 EMC_OENx_N Out LOW/2 EMC_RW_N Out Level 2 Inter-Integrated Circuit (I C) Peripherals ...
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Polarity/ Name Type Bus Size SPI_1_DO Out 1 SPI_1_SS Out 1 Universal Asynchronous Receiver/Transmitter (UART) Peripherals UART_0_RXD In 1 UART_0_TXD Out 1 UART_1_RXD In 1 UART_1_TXD Out 1 Ethernet MAC MAC_CLK In Rise MAC_CRSDV In High MAC_MDC Out Rise MAC_MDIO ...
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Pin Descriptions Analog Front-End (AFE) Name Type ABPS0 In SCB 0 / active bipolar prescaler input 1. See the Active Bipolar Prescaler (ABPS) section in the Programmable Analog User’s ABPS1 In SCB 0 / active bipolar prescaler Input 2 ABPS2 ...
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Name Type TM0 In SCB 0 / low side of current monitor / comparator Negative input / high side of temperature monitor. See the Temperature Monitor section. TM1 In SCB 1 / low side of current monitor / comparator. Negative ...
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Pin Descriptions Analog Front-End Pin-Level Function Multiplexing Table 5-2 describes the relationships between the various internal signals found in the analog front-end (AFE) and how they are multiplexed onto the external package pins. Note that, in general, only one function ...
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Table 5-2 • Relationships Between Signals in the Analog Front-End ADC Dir.-In Pin Channel Option Prescaler SDD2 ADC2_CH15 TM0 ADC0_CH4 Yes TM1 ADC0_CH8 Yes TM2 ADC1_CH4 Yes TM3 ADC1_CH8 Yes TM4 ADC2_CH4 Yes Notes: 1. ABPSx_IN: Input to active bipolar ...
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... Pin Descriptions Pin Assignment Tables 288-Pin CSP Note: Bottom view For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx Ball Pad Corner visio n 6 ...
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Pin Number A2F060 Function A1 VCCFPGAIOB0 A2 GNDQ A3 EMC_CLK/IO00NDB0V0 A4 EMC_RW_N/IO00PDB0V0 A5 GND A6 EMC_CS1_N/IO01PDB0V0 A7 EMC_CS0_N/IO01NDB0V0 A8 EMC_AB[0]/IO04NPB0V0 A9 VCCFPGAIOB0 A10 EMC_AB[4]/IO06NDB0V0 A11 EMC_AB[8]/IO08NPB0V0 A12 EMC_AB[14]/IO11NPB0V0 A13 GND A14 EMC_AB[18]/IO13NDB0V0 A15 EMC_AB[24]/IO16NDB0V0 A16 EMC_AB[25]/IO16PDB0V0 A17 VCCFPGAIOB0 A18 EMC_AB[20]/IO14NDB0V0 ...
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Pin Descriptions Pin Number AA16 AA17 AA18 AA19 AA20 AA21 B1 B21 C1 EMC_DB[15]/IO71PDB5V0 EMC_AB[1]/IO04PPB0V0 C7 C8 EMC_OEN0_N/IO03NDB0V0 C9 EMC_AB[2]/IO05NDB0V0 C10 EMC_AB[5]/IO06PDB0V0 C11 C12 EMC_AB[9]/IO08PPB0V0 C13 EMC_AB[15]/IO11PPB0V0 C14 EMC_AB[19]/IO13PDB0V0 C15 C16 EMC_AB[22]/IO15NDB0V0 C17 EMC_AB[23]/IO15PDB0V0 C18 C19 ...
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Pin Number A2F060 Function E8 EMC_OEN1_N/IO03PDB0V0 E9 EMC_AB[3]/IO05PDB0V0 E10 EMC_AB[10]/IO09NDB0V0 E11 EMC_AB[7]/IO07PDB0V0 E12 EMC_AB[13]/IO10PDB0V0 E13 EMC_AB[16]/IO12NDB0V0 E14 EMC_AB[17]/IO12PDB0V0 E15 GCB0/IO27NDB1V0 E16 GCB1/IO27PDB1V0 E17 GCB2/IO24PDB1V0 E19 GCA0/IO28NDB1V0 E21 IO28PDB1V0 F1 VCCFPGAIOB5 F3 GFB2/IO68NDB5V0 F5 GFA2/IO68PDB5V0 F6 EMC_DB[11]/IO69PDB5V0 F7 GND F8 NC ...
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Pin Descriptions Pin Number G17 G19 GDC0/IO29NDB1V0 G21 H1 EMC_DB[9]/IO63PPB5V0 EMC_DB[7]/IO62PDB5V0 H8 H9 H10 H11 H12 H13 H14 H16 H17 H19 H21 J1 EMC_DB[4]/IO61NPB5V0 J3 EMC_DB[8]/IO63NPB5V0 J5 EMC_DB[1]/IO59PDB5V0 J6 EMC_DB[6]/IO62NDB5V0 J10 J11 J12 J13 ...
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Pin Number A2F060 Function K3 EMC_DB[5]/IO61PPB5V0 K5 EMC_DB[0]/IO59NDB5V0 K6 EMC_DB[3]/IO60PPB5V0 K8 GND K9 VCC K10 GND K11 VCC K12 GND K13 VCC K14 GND K16 LPXOUT K17 GNDLPXTAL K19 GNDMAINXTAL K21 MAINXIN L1 GNDRCOSC L3 VCCFPGAIOB5 L5 EMC_DB[2]/IO60NPB5V0 L6 GNDQ ...
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Pin Descriptions Pin Number M12 M13 M14 M16 M17 M19 M21 GPIO_4/IO43RSB4V0 N6 GPIO_8/IO39RSB4V0 N7 GPIO_9/IO38RSB4V0 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N19 N21 P1 P3 GPIO_7/IO40RSB4V0 P5 GPIO_6/IO41RSB4V0 P10 ...
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Pin Number A2F060 Function P17 I2C_0_SCL/GPIO_23 P19 VCCMSSIOB2 P21 GND R1 IO49RSB4V0 R3 IO52RSB4V0 R5 IO56RSB4V0 R6 IO51RSB4V0 R9 GNDA R13 GNDA R16 UART_1_RXD/GPIO_29 R17 UART_1_TXD/GPIO_28 R19 I2C_0_SDA/GPIO_22 R21 I2C_1_SDA/GPIO_30 T1 GND IO50RSB4V0 T7 NC ...
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Pin Descriptions Pin Number U9 U10 U11 U12 U13 U14 U15 SPI_1_CLK/GPIO_26 U16 SPI_0_CLK/GPIO_18 U17 SPI_0_SS/GPIO_19 U19 U21 SPI_1_DO/GPIO_24 V1 V3 V19 SPI_1_DI/GPIO_25 V21 W10 W11 W12 W13 W14 W15 W16 W17 ...
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Pin Number A2F200 Function A1 VCCFPGAIOB0 A2 GNDQ A3 EMC_CLK/GAA0/IO00NDB0V0 A4 EMC_RW_N/GAA1/IO00PDB0V0 A5 GND A6 EMC_CS1_N/GAB1/IO01PDB0V0 A7 EMC_CS0_N/GAB0/IO01NDB0V0 A8 EMC_AB[0]/IO04NPB0V0 A9 VCCFPGAIOB0 A10 EMC_AB[4]/IO06NDB0V0 A11 EMC_AB[8]/IO08NPB0V0 A12 EMC_AB[14]/IO11NPB0V0 A13 GND A14 EMC_AB[18]/IO13NDB0V0 A15 EMC_AB[24]/IO16NDB0V0 A16 EMC_AB[25]/IO16PDB0V0 A17 VCCFPGAIOB0 A18 EMC_AB[20]/IO14NDB0V0 ...
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Pin Descriptions Pin Number AA16 AA17 AA18 AA19 AA20 AA21 B1 B21 C1 EMC_DB[15]/GAA2/IO71PDB5V0 EMC_OEN0_N/IO03NDB0V0 C9 C10 C11 C12 C13 C14 EMC_AB[19]/IO13PDB0V0 C15 C16 EMC_AB[22]/IO15NDB0V0 C17 EMC_AB[23]/IO15PDB0V0 C18 C19 C21 D1 EMC_DB[14]/GAB2/IO71NDB5V0 D3 D19 ...
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Pin Number A2F200 Function E8 EMC_OEN1_N/IO03PDB0V0 E9 EMC_AB[3]/IO05PDB0V0 E10 EMC_AB[10]/IO09NDB0V0 E11 EMC_AB[7]/IO07PDB0V0 E12 EMC_AB[13]/IO10PDB0V0 E13 EMC_AB[16]/IO12NDB0V0 E14 EMC_AB[17]/IO12PDB0V0 E15 GCB0/IO27NDB1V0 E16 GCB1/IO27PDB1V0 E17 GCB2/IO24PDB1V0 E19 GCA0/IO28NDB1V0 E21 GCA1/IO28PDB1V0 F1 VCCFPGAIOB5 F3 GFB2/IO68NDB5V0 F5 GFA2/IO68PDB5V0 F6 EMC_DB[11]/IO69PDB5V0 F7 GND F8 GFC1/IO66PPB5V0 ...
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Pin Descriptions Pin Number G17 G19 G21 H1 EMC_DB[9]/GEC1/IO63PPB5V0 EMC_DB[7]/GEB1/IO62PDB5V0 H8 H9 H10 H11 H12 H13 H14 H16 H17 H19 H21 J1 EMC_DB[4]/GEA0/IO61NPB5V0 J3 EMC_DB[8]/GEC0/IO63NPB5V0 J5 EMC_DB[1]/GEB2/IO59PDB5V0 J6 EMC_DB[6]/GEB0/IO62NDB5V0 J10 J11 J12 J13 J14 ...
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Pin Number A2F200 Function K3 EMC_DB[5]/GEA1/IO61PPB5V0 K5 EMC_DB[0]/GEA2/IO59NDB5V0 K6 EMC_DB[3]/GEC2/IO60PPB5V0 K8 GND K9 VCC K10 GND K11 VCC K12 GND K13 VCC K14 GND K16 LPXOUT K17 GNDLPXTAL K19 GNDMAINXTAL K21 MAINXIN L1 GNDRCOSC L3 VCCFPGAIOB5 L5 EMC_DB[2]/IO60NPB5V0 L6 GNDQ ...
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Pin Descriptions Pin Number M12 M13 M14 M16 M17 M19 M21 N10 N11 N12 N13 N14 N15 N16 N17 N19 N21 P10 P11 P12 P13 P14 P16 ...
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Pin Number A2F200 Function P17 I2C_0_SCL/GPIO_23 P19 VCCMSSIOB2 P21 GND R1 MAC_MDIO/IO49RSB4V0 R3 MAC_TXEN/IO52RSB4V0 R5 MAC_TXD[0]/IO56RSB4V0 R6 MAC_CRSDV/IO51RSB4V0 R9 GNDA R13 GNDA R16 UART_1_RXD/GPIO_29 R17 UART_1_TXD/GPIO_28 R19 I2C_0_SDA/GPIO_22 R21 I2C_1_SDA/GPIO_30 T1 GND T3 MAC_TXD[1]/IO55RSB4V0 T5 MAC_RXD[1]/IO53RSB4V0 T6 MAC_RXER/IO50RSB4V0 T7 CM1 ...
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Pin Descriptions Pin Number U9 U10 U11 U12 U13 U14 U15 U16 U17 U19 U21 V1 V3 V19 V21 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W21 Y1 Y21 ...
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... PQFP 208 1 Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. SmartFusion Intelligent Mixed Signal FPGAs 208-Pin PQFP ...
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Pin Descriptions Pin Number EMC_DB[15]/GAA2/IO71PDB5V0 5 EMC_DB[14]/GAB2/IO71NDB5V0 6 EMC_DB[13]/GAC2/IO70PDB5V0 7 EMC_DB[12]/IO70NDB5V0 EMC_DB[11]/IO69PDB5V0 12 EMC_DB[10]/IO69NDB5V0 EMC_DB[9]/GEC1/IO63PDB5V0 17 EMC_DB[8]/GEC0/IO63NDB5V0 18 EMC_DB[7]/GEB1/IO62PDB5V0 19 EMC_DB[6]/GEB0/IO62NDB5V0 20 EMC_DB[5]/GEA1/IO61PDB5V0 21 EMC_DB[4]/GEA0/IO61NDB5V0 ...
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Pin Number A2F200 36 MAC_MDIO/IO49RSB4V0 37 MAC_TXEN/IO52RSB4V0 38 MAC_CRSDV/IO51RSB4V0 39 MAC_RXER/IO50RSB4V0 40 GND 41 VCCMSSIOB4 42 VCC 43 MAC_TXD[0]/IO56RSB4V0 44 MAC_TXD[1]/IO55RSB4V0 45 MAC_RXD[0]/IO54RSB4V0 46 MAC_RXD[1]/IO53RSB4V0 47 MAC_CLK 48 GNDSDD0 49 VCC33SDD0 50 VCC15A 51 PCAP 52 NCAP 53 VCC33AP 54 ...
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Pin Descriptions Pin Number 100 101 102 103 104 105 106 107 ...
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Pin Number A2F200 108 SPI_0_SS/GPIO_19 109 UART_0_RXD/GPIO_21 110 UART_0_TXD/GPIO_20 111 UART_1_RXD/GPIO_29 112 UART_1_TXD/GPIO_28 113 VCC 114 VCCMSSIOB2 115 GND 116 I2C_1_SDA/GPIO_30 117 I2C_1_SCL/GPIO_31 118 I2C_0_SDA/GPIO_22 119 I2C_0_SCL/GPIO_23 120 GNDENVM 121 VCCENVM 122 JTAGSEL 123 TCK 124 TDI 125 TMS 126 ...
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Pin Descriptions Pin Number 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 EMC_AB[25]/IO16PDB0V0 165 EMC_AB[24]/IO16NDB0V0 166 EMC_AB[23]/IO15PDB0V0 167 EMC_AB[22]/IO15NDB0V0 168 EMC_AB[21]/IO14PDB0V0 169 EMC_AB[20]/IO14NDB0V0 170 EMC_AB[19]/IO13PDB0V0 171 ...
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Pin Number A2F200 179 EMC_AB[13]/IO10PDB0V0 180 EMC_AB[12]/IO10NDB0V0 181 EMC_AB[11]/IO09PDB0V0 182 EMC_AB[10]/IO09NDB0V0 183 EMC_AB[9]/IO08PDB0V0 184 EMC_AB[8]/IO08NDB0V0 185 EMC_AB[7]/IO07PDB0V0 186 EMC_AB[6]/IO07NDB0V0 187 VCCFPGAIOB0 188 GND 189 VCC 190 EMC_AB[5]/IO06PDB0V0 191 EMC_AB[4]/IO06NDB0V0 192 EMC_AB[3]/IO05PDB0V0 193 EMC_AB[2]/IO05NDB0V0 194 EMC_AB[1]/IO04PDB0V0 195 EMC_AB[0]/IO04NDB0V0 196 EMC_OEN1_N/IO03PDB0V0 197 ...
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... Pin Descriptions 256-Pin FBGA Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx Ball Pad Corner visio ...
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Pin Number A2F060 Function A1 GND A2 VCCFPGAIOB0 A3 EMC_AB[0]/IO04NDB0V0 A4 EMC_AB[1]/IO04PDB0V0 A5 GND A6 EMC_AB[3]/IO05PDB0V0 A7 EMC_AB[5]/IO06PDB0V0 A8 VCCFPGAIOB0 A9 GND A10 EMC_AB[14]/IO11NDB0V0 A11 EMC_AB[15]/IO11PDB0V0 A12 GND A13 EMC_AB[20]/IO14NDB0V0 A14 EMC_AB[24]/IO16NDB0V0 A15 VCCFPGAIOB0 A16 GND B1 EMC_DB[15]/IO71PDB5V0 B2 GND ...
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Pin Descriptions Pin Number C2 C3 EMC_BYTEN[0]/IO02NDB0V0 C4 C5 EMC_CS0_N/IO01NDB0V0 C6 EMC_CS1_N/IO01PDB0V0 C7 C8 EMC_AB[8]/IO08NDB0V0 C9 EMC_AB[11]/IO09PDB0V0 C10 C11 EMC_AB[17]/IO12PDB0V0 C12 EMC_AB[19]/IO13PDB0V0 C13 C14 C15 C16 EMC_CLK/IO00NDB0V0 D6 EMC_RW_N/IO00PDB0V0 D7 EMC_AB[6]/IO07NDB0V0 D8 EMC_AB[7]/IO07PDB0V0 D9 EMC_AB[10]/IO09NDB0V0 ...
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Pin Number A2F060 Function E3 GFA2/IO68PDB5V0 E4 EMC_DB[10]/IO69NPB5V0 E5 GNDQ E6 GND E7 VCCFPGAIOB0 E8 GND E9 VCCFPGAIOB0 E10 GND E11 VCCFPGAIOB0 E12 GCA1/IO28PDB1V0 E13 VCCFPGAIOB1 E14 GCB1/IO27PDB1V0 E15 GDC1/IO29PDB1V0 E16 IO29NDB1V0 F1 EMC_DB[9]/IO63PDB5V0 F2 GND F3 GFB2/IO68NDB5V0 F4 VCCFPGAIOB5 ...
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Pin Descriptions Pin Number G10 G11 G12 G13 G14 G15 G16 H1 H2 EMC_DB[5]/IO61PPB5V0 H3 H4 EMC_DB[1]/IO59PDB5V0 H5 EMC_DB[0]/IO59NDB5V0 H10 H11 H12 H13 H14 H15 H16 J1 EMC_DB[4]/IO61NPB5V0 J2 EMC_DB[3]/IO60PDB5V0 ...
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Pin Number A2F060 Function J5 GNDQ J6 GND J7 VCC J8 GND J9 VCC J10 GND J11 VCCMSSIOB2 J12 I2C_0_SCL/GPIO_23 J13 I2C_0_SDA/GPIO_22 J14 I2C_1_SCL/GPIO_31 J15 VCCMSSIOB2 J16 I2C_1_SDA/GPIO_30 K1 IO49RSB4V0 K2 IO48RSB4V0 K3 VCCMSSIOB4 K4 MSS_RESET_N K5 VCCRCOSC K6 VCCMSSIOB4 ...
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Pin Descriptions Pin Number L10 L11 L12 L13 L14 L15 L16 M10 M11 M12 M13 M14 M15 M16 Note: Shading denotes ...
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Pin Number A2F060 Function VCC33ADC1 N9 ADC5 N10 CM3 N11 GNDAQ N12 VAREFOUT N13 NC N14 NC N15 GND N16 SPI_0_DO/GPIO_16 P1 GNDSDD0 P2 VCC33SDD0 P3 VCC33N P4 GNDA P5 GNDAQ ...
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Pin Descriptions Pin Number R8 R9 R10 R11 R12 R13 R14 R15 R16 T10 T11 T12 T13 T14 T15 T16 Note: Shading denotes pins that do not have completely identical functions ...
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Pin Number A2F200 Function A1 GND A2 VCCFPGAIOB0 A3 EMC_AB[0]/IO04NDB0V0 A4 EMC_AB[1]/IO04PDB0V0 A5 GND A6 EMC_AB[3]/IO05PDB0V0 A7 EMC_AB[5]/IO06PDB0V0 A8 VCCFPGAIOB0 A9 GND A10 EMC_AB[14]/IO11NDB0V0 A11 EMC_AB[15]/IO11PDB0V0 A12 GND A13 EMC_AB[20]/IO14NDB0V0 A14 EMC_AB[24]/IO16NDB0V0 A15 VCCFPGAIOB0 A16 GND B1 EMC_DB[15]/GAA2/IO71PDB5V0 B2 GND ...
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Pin Number A2F200 Function C2 VCCPLL C3 EMC_BYTEN[0]/GAC0/IO02NDB0V0 C4 VCCFPGAIOB0 C5 EMC_CS0_N/GAB0/IO01NDB0V0 C6 EMC_CS1_N/GAB1/IO01PDB0V0 C7 C8 EMC_AB[8]/IO08NDB0V0 C9 EMC_AB[11]/IO09PDB0V0 C10 VCCFPGAIOB0 C11 EMC_AB[17]/IO12PDB0V0 C12 EMC_AB[19]/IO13PDB0V0 C13 C14 GBA2/IO20PPB1V0 C15 GCA2/IO23PDB1V0 C16 IO23NDB1V0 D1 VCCFPGAIOB5 D2 VCOMPLA EMC_CLK/GAA0/IO00NDB0V0 ...
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Pin Number A2F200 Function E3 GFA2/IO68PDB5V0 E4 EMC_DB[10]/IO69NPB5V0 E5 GNDQ E6 GND E7 VCCFPGAIOB0 E8 GND E9 VCCFPGAIOB0 E10 GND E11 VCCFPGAIOB0 E12 GCA1/IO28PDB1V0 E13 VCCFPGAIOB1 E14 GCB1/IO27PDB1V0 E15 GDC1/IO29PDB1V0 E16 GDC0/IO29NDB1V0 F1 EMC_DB[9]/GEC1/IO63PDB5V0 F2 GND F3 GFB2/IO68NDB5V0 F4 VCCFPGAIOB5 ...
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Pin Descriptions Pin Number G10 G11 G12 G13 G14 G15 G16 H1 H2 EMC_DB[5]/GEA1/IO61PPB5V0 H3 H4 EMC_DB[1]/GEB2/IO59PDB5V0 H5 EMC_DB[0]/GEA2/IO59NDB5V0 H10 H11 H12 H13 H14 H15 H16 J1 EMC_DB[4]/GEA0/IO61NPB5V0 J2 EMC_DB[3]/GEC2/IO60PDB5V0 ...
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Pin Number A2F200 Function J5 GNDQ J6 GND J7 VCC J8 GND J9 VCC J10 GND J11 VCCMSSIOB2 J12 I2C_0_SCL/GPIO_23 J13 I2C_0_SDA/GPIO_22 J14 I2C_1_SCL/GPIO_31 J15 VCCMSSIOB2 J16 I2C_1_SDA/GPIO_30 K1 MAC_MDIO/IO49RSB4V0 K2 MAC_MDC/IO48RSB4V0 K3 VCCMSSIOB4 K4 MSS_RESET_N K5 VCCRCOSC K6 VCCMSSIOB4 ...
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Pin Descriptions Pin Number L10 L11 L12 L13 L14 L15 L16 M1 MAC_TXD[0]/IO56RSB4V0 M2 MAC_TXD[1]/IO55RSB4V0 M3 MAC_RXD[0]/IO54RSB4V0 M10 M11 M12 M13 M14 M15 M16 N1 MAC_RXD[1]/IO53RSB4V0 ...
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Pin Number A2F200 Function N7 GND33ADC0 N8 VCC33ADC1 N9 ADC5 N10 CM3 N11 GNDAQ N12 VAREFOUT N13 GNDSDD1 N14 VCC33SDD1 N15 GND N16 SPI_0_DO/GPIO_16 P1 GNDSDD0 P2 VCC33SDD0 P3 VCC33N P4 GNDA P5 GNDAQ P6 CM1 P7 ADC2 P8 VCC15ADC0 ...
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Pin Descriptions Pin Number R8 R9 R10 R11 R12 R13 R14 R15 R16 T10 T11 T12 T13 T14 T15 T16 Note: Shading denotes pins that do not have completely identical functions ...
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... FBGA Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. SmartFusion Intelligent Mixed Signal FPGAs A1 Ball Pad Corner ...
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Pin Descriptions Pin Number A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 ...
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Pin Number A2F200 Function AA15 AA16 MAINXIN AA17 MAINXOUT AA18 AA19 LPXOUT AA20 AA21 AA22 SPI_1_CLK/GPIO_26 AB1 AB2 GPIO_13/IO36RSB4V0 AB3 GPIO_14/IO35RSB4V0 AB4 AB5 AB6 AB7 AB8 AB9 GND15ADC0 AB10 VCC33ADC1 AB11 VAREF1 AB12 AB13 AB14 AB15 GNDAQ AB16 GNDMAINXTAL AB17 ...
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Pin Descriptions Pin Number EMC_BYTEN[0]/GAC0/IO02NDB0V0 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 EMC_BYTEN[1]/GAC1/IO02PDB0V0 C10 C11 C12 C13 C14 C15 C16 C17 C18 ...
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Pin Number A2F200 Function C21 GBC2/IO21PDB1V0 C22 GBB2/IO20NDB1V0 D1 D2 EMC_DB[12]/IO70NDB5V0 D3 EMC_DB[13]/GAC2/IO70PDB5V0 D10 EMC_OEN0_N/IO03NDB0V0 D11 EMC_AB[10]/IO09NDB0V0 D12 EMC_AB[11]/IO09PDB0V0 D13 EMC_AB[9]/IO08PDB0V0 D14 D15 GBC1/IO17PPB0V0 D16 EMC_AB[25]/IO16PDB0V0 D17 D18 GBA1/IO19PPB0V0 D19 D20 D21 IO21NDB1V0 D22 ...
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Pin Descriptions Pin Number E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 ...
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Pin Number A2F200 Function G5 EMC_DB[11]/IO69PPB5V0 VCCFPGAIOB0 G10 G11 VCCFPGAIOB0 G12 G13 VCCFPGAIOB0 G14 G15 VCCFPGAIOB0 G16 G17 G18 G19 GCA2/IO23PDB1V0 G20 IO24NDB1V0 G21 GCB2/IO24PDB1V0 G22 H1 EMC_DB[7]/GEB1/IO62PDB5V0 H2 VCCFPGAIOB5 H3 EMC_DB[8]/GEC0/IO63NDB5V0 H4 H5 GFC0/IO66NPB5V0 H6 ...
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Pin Descriptions Pin Number H19 H20 H21 H22 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 K10 ...
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Pin Number A2F200 Function K11 K12 K13 K14 K15 K16 VCCFPGAIOB1 K17 K18 GDA1/IO31PDB1V0 K19 GDA0/IO31NDB1V0 K20 GDC1/IO29PDB1V0 K21 GDC0/IO29NDB1V0 K22 VCCFPGAIOB5 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 ...
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Pin Descriptions Pin Number M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 N10 N11 N12 N13 N14 N15 N16 ...
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Pin Number A2F200 Function N17 N18 VCCFPGAIOB1 N19 VCCENVM N20 GNDENVM N21 N22 GNDRCOSC P10 P11 P12 P13 P14 P15 P16 VCCFPGAIOB1 P17 P18 P19 P20 P21 P22 R1 MSS_RESET_N R2 ...
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Pin Descriptions Pin Number R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...
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Pin Number A2F200 Function U1 U2 GPIO_5/IO42RSB4V0 U3 GPIO_10/IO58RSB4V0 U4 VCCMSSIOB4 U5 MAC_RXD[1]/IO53RSB4V0 U6 U7 VCC33AP U8 VCC33N U9 U10 VAREF0 U11 GND33ADC1 U12 U13 U14 U15 GNDVAREF U16 VCC33SDD1 U17 SPI_0_DO/GPIO_16 U18 UART_0_RXD/GPIO_21 U19 VCCMSSIOB2 U20 I2C_1_SCL/GPIO_31 U21 I2C_0_SCL/GPIO_23 ...
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Pin Descriptions Pin Number V15 V16 V17 V18 V19 V20 V21 V22 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 ...
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Pin Number A2F200 Function Y7 Y8 GNDTM0 Y9 Y10 VCC15ADC0 Y11 Y12 Y13 Y14 Y15 Y16 VCCMAINXTAL Y17 Y18 Y19 VCC33A Y20 SPI_0_SS/GPIO_19 Y21 VCCMSSIOB2 Y22 UART_0_TXD/GPIO_20 Note: Shading denotes pins that do not have completely identical functions from density ...
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Datasheet Information List of Changes The following table lists critical changes that were made in each revision of the SmartFusion datasheet. Revision Revision 6 The "PQ208" package was added to product tables and (March 2011) A2F200 and A2F500 ...
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Datasheet Information Revision Revision 5 Table 2-2 • Analog Maximum Ratings (December 2010) voltage (relative to ground) was changed from –11 to –0.3 (SAR 28219). Table 2-7 • Temperature and Voltage Derating Factors for Timing Delays to change the values ...
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Revision Revision 4 Table 2-8 • Quiescent Supply Current Characteristics (September moved to a column of its own with new values. VCCENVM was added to the table. 2010) Standby mode for VJTAG and VPP was changed from ...
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Datasheet Information Revision Revision 3 A note was added to (continued stating that "one of the CCC outputs (GLA0) is used as an MSS clock and is out_CCC limited to 100 MHz (maximum) by software" (SAR 26388). Table ...
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Revision Revision 2 Embedded nonvolatile flash memory (eNVM) was changed from "64 to 512 Kbytes" to (May 2010) "128 to 512 Kbytes" in the "SmartFusion Family Product Table" The main oscillator range of values was changed to "32 KHz to ...
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Datasheet Information Revision Revision 0 Table 2-1 • Absolute Maximum (continued) Table 2-3 • Recommended Operating Conditions Device names were updated in Table 2-8 • Quiescent Supply Current Characteristics Table 2-10 • Summary of I/O Input Buffer Power (per pin) ...
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Revision Draft B The "Digital I/Os" section was renamed to the (December 2009) and information was added regarding digital and analog VCC. The "SmartFusion Family Product Table" section were revised. The terminology for the analog blocks was changed to "programmable ...
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... A reliability report covering all of the SoC Products Group’s products http://www.actel.com/documents/ORT_Report.pdf. Microsemi SoC Products Group also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local SoC Products Group sales office for additional reliability information. ...
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Microsemmi Corporate Headquarters 2381 Morse Avenue, Irvine, CA 92614 Phone: 949-221-7100·Fax: 949-756-0308 www.microsemi.com Microsemi Corporation (NASDAQ: MSCC) offers the industry’s most comprehensive portfolio of semiconductor technology. Committed to solving the most critical system challenges, Microsemi’s products include high-performance, high-reliability analog ...