A2F500M3G-FGG256 Actel, A2F500M3G-FGG256 Datasheet - Page 26

• Manufacturer Part Number: A2F500M3G-FGG256
• Description: FPGA - Field Programmable Gate Array 500K System Gates
• Manufacturer: Actel

Specifications of A2F500M3G-FGG256

• Processor Series: A2F500
• Core: ARM Cortex M3
• Number Of Logic Blocks: 24
• Maximum Operating Frequency: 100 MHz
• Number Of Programmable I/os: 117
• Data Ram Size: 64 KB
• Delay Time: 50 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.5 V
• Number Of Gates: 500000
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SmartFusion DC and Switching Characteristics
2- 14
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For more
accurate and detailed power estimations, use the SmartPower tool in the Libero IDE software.
The power calculation methodology described below uses the following variables:
The calculation should be repeated for each clock domain defined in the design.
Methodology
Total Power Consumption—P
Total Static Power Consumption—P
Total Dynamic Power Consumption—P
•
•
•
•
•
•
•
•
•
•
•
SoC Mode, Standby Mode, and Time Keeping Mode.
P
SoC Mode
P
Standby Mode
P
Time Keeping Mode
P
SoC Mode
P
P
TOTAL
STAT
STAT
STAT
DYN
XTL-OSC
The number of PLLs/CCCs as well as the number and the frequency of each output clock
generated
The number of combinatorial and sequential cells used in the design
The internal clock frequencies
The number and the standard of I/O pins used in the design
The number of RAM blocks used in the design
The number of eNVM blocks used in the design
The analog block used in the design, including the temperature monitor, current monitor, ABPS,
sigma-delta DAC, comparator, low power crystal oscillator, RC oscillator and the main crystal
oscillator
Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in
page
Enable rates of output buffers—guidelines are provided for typical applications in
page
Read rate and write rate to the memory—guidelines are provided for typical applications in
Table 2-17 on page
Read rate to the eNVM blocks
P
P
N
N
N
N
STAT
DYN
eNVM-BLOCKS
INPUTS
OUTPUTS
PLLS
= P
= P
= P
= P
= P
2-18.
2-18.
CLOCK
is the total dynamic power consumption.
DC1
DC2
DC3
+ P
is the total static power consumption.
is the number of PLLs available in the device.
STAT
is the number of I/O input buffers used in the design.
RC-OSC
+ (N
is the number of I/O output buffers used in the design.
+ P
+ P
eNVM-BLOCKS
is the number of eNVM blocks available in the device.
S-CELL
DYN
+ P
2-18.
AB
+ P
+ P
C-CELL
LPXTAL-OSC
TOTAL
* P
DC4
+ P
) + (N
STAT
NET
R e visio n 6
+ P
DYN
INPUTS
+ P
MSS
INPUTS
* P
DC7
+ P
) + (N
OUTPUTS
OUTPUTS
+ P
MEMORY
* P
DC8
) + (N
+ P
PLL
PLLS
Table 2-16 on
Table 2-17 on
+ P
* P
eNVM
DC9
+
)