A2F500M3G-FGG256 Actel, A2F500M3G-FGG256 Datasheet - Page 71
![FPGA - Field Programmable Gate Array 500K System Gates](/photos/16/14/161496/lpsilverchip_sml.jpg)
A2F500M3G-FGG256
Manufacturer Part Number
A2F500M3G-FGG256
Description
FPGA - Field Programmable Gate Array 500K System Gates
Manufacturer
Actel
Datasheet
1.A2F500M3G-FGG256.pdf
(192 pages)
Specifications of A2F500M3G-FGG256
Processor Series
A2F500
Core
ARM Cortex M3
Number Of Logic Blocks
24
Maximum Operating Frequency
100 MHz
Number Of Programmable I/os
117
Data Ram Size
64 KB
Delay Time
50 ns
Supply Voltage (max)
3.6 V
Supply Current
2 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.5 V
Number Of Gates
500000
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A2F500M3G-FGG256
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
A2F500M3G-FGG256I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A2F500M3G-FGG256I
Manufacturer:
MICROSEMI/美高森美
Quantity:
20 000
Global Resource Characteristics
Figure 2-27 • Example of Global Tree Use in an A2F200 Device for Clock Routing
CCC
A2F200 Clock Tree Topology
Clock delays are device-specific.
global tree presented in
is used to drive all D-flip-flops in the device.
Figure 2-27
Figure 2-27
is driven by a CCC located on the west side of the A2F200 device. It
R e v i s i o n 6
is an example of a global tree used for clock routing. The
SmartFusion Intelligent Mixed Signal FPGAs
Central
Global Rib
VersaTile
Rows
Global Spine
2- 59