A2F500M3G-FGG256 Actel, A2F500M3G-FGG256 Datasheet - Page 28

• Manufacturer Part Number: A2F500M3G-FGG256
• Description: FPGA - Field Programmable Gate Array 500K System Gates
• Manufacturer: Actel

Specifications of A2F500M3G-FGG256

• Processor Series: A2F500
• Core: ARM Cortex M3
• Number Of Logic Blocks: 24
• Maximum Operating Frequency: 100 MHz
• Number Of Programmable I/os: 117
• Data Ram Size: 64 KB
• Delay Time: 50 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.5 V
• Number Of Gates: 500000
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SmartFusion DC and Switching Characteristics
2- 16
1.The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the
PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output
clock in the formula output clock by adding its corresponding contribution (P
contribution.
I/O Input Buffer Dynamic Contribution—P
I/O Output Buffer Dynamic Contribution—P
FPGA Fabric SRAM Dynamic Contribution—P
PLL/CCC Dynamic Contribution—P
Standby Mode and Time Keeping Mode
P
SoC Mode
P
Where:
Standby Mode and Time Keeping Mode
P
SoC Mode
P
Where:
Standby Mode and Time Keeping Mode
P
SoC Mode
P
Where:
Standby Mode and Time Keeping Mode
P
SoC Mode
P
NET
INPUTS
INPUTS
OUTPUTS
OUTPUTS
MEMORY
MEMORY
PLL
N
α
F
N
α
β
F
N
F
β
page
β
page
F
F
F
CLK
CLK
READ-CLOCK
WRITE-CLOCK
CLKIN
CLKOUT
INPUTS
OUTPUTS
1
BLOCKS
2
3
= P
2
2
= 0 W
is the I/O buffer enable rate—guidelines are provided in
is the I/O buffer toggle rate—guidelines are provided in
is the I/O buffer toggle rate—guidelines are provided in
is the RAM enable rate for read operations—guidelines are provided in
the RAM enable rate for write operations—guidelines are provided in
AC13
= N
= 0 W
is the global clock signal frequency.
is the global clock signal frequency.
2-18.
2-18.
= (N
= 0 W
= N
= 0 W
is the input clock frequency.
INPUTS
is the number of I/O input buffers used in the design.
is the output clock frequency.
is the number of RAM blocks used in the design.
* F
OUTPUTS
is the number of I/O output buffers used in the design.
BLOCKS
CLKOUT
is the memory read clock frequency.
is the memory write clock frequency.
* (
α
* P
* (
2
/ 2) * P
AC11
α
2
/ 2) *
*
β
AC9
2
β
* F
* F
1
* P
READ-CLOCK
PLL
CLK
AC10
R e visio n 6
1
INPUTS
* F
OUTPUTS
CLK
) + (N
MEMORY
BLOCKS
AC14
Table 2-16 on page
Table 2-16 on page
Table 2-17 on page
* P
* F
AC12
CLKOUT
*
β
3
product) to the total PLL
* F
WRITE-CLOCK
2-18.
2-18.
2-18.
Table 2-17 on
Table 2-17 on
)