AFS250-PQG208 Actel, AFS250-PQG208 Datasheet - Page 145
AFS250-PQG208
Manufacturer Part Number
AFS250-PQG208
Description
FPGA - Field Programmable Gate Array 250K System Gates
Manufacturer
Actel
Datasheet
1.AFS600-PQG208.pdf
(330 pages)
Specifications of AFS250-PQG208
Processor Series
AFS250
Core
IP Core
Maximum Operating Frequency
1098.9 MHz
Number Of Programmable I/os
93
Data Ram Size
36864
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
250 K
Package / Case
PQFP-208
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
Quantity
Price
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Part Number:
AFS250-PQG208
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NXP
Quantity:
8 000
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Part Number:
AFS250-PQG208I
Manufacturer:
MPS
Quantity:
12 000
Company:
Part Number:
AFS250-PQG208I
Manufacturer:
Microsemi SoC
Quantity:
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Part Number:
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Figure 2-95 • ACM Write Waveform
Figure 2-96 • ACM Read Waveform
ACMADDRESS
1. When addressing the RTC addresses (i.e., ACMADDR 64 to 89), there is no timing generator, and the rc_osc, byte_en, and
ACMADDRESS
ACMWDATA
ACMRDATA
ACMWEN
ACMCLK
ACMCLK
aq_wen signals have no impact.
Table 2-51 • ACM Address Decode Table for Analog Quad (continued)
ACM Characteristics
ACMADDR [7:0] in
Decimal
73
74
75
76
80
81
82
83
84
88
Note:
t
t
t
SUEACM
SUDACM
SUAACM
ACMADDR bytes 1 to 40 pertain to the Analog Quads; bytes 64 to 89 pertain to the RTC.
D0
A0
A0
t
CLKQACM
t
t
t
HDACM
HEACM
HAACM
t
RD0
MPWCLKACM
MATCHBITS0
MATCHBITS1
MATCHBITS2
MATCHBITS3
MATCHBITS4
MATCHREG1
MATCHREG2
MATCHREG3
MATCHREG4
CTRL_STAT
1
Name
R e v i s i o n 1
Control (write) / Status (read) register
Individual match bits 23:16
Individual match bits 31:24
Individual match bits 39:32
Individual match bits 15:8
Match register bits 23:16
Match register bits 31:24
Match register bits 39:32
Individual match bits 7:0
Match register bits 15:8
Description
bits 7:0
Actel Fusion Family of Mixed Signal FPGAs
D1
A1
A1
RD1
Associated
Peripheral
RTC
RTC
RTC
RTC
RTC
RTC
RTC
RTC
RTC
RTC
2- 129
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