AFS250-PQG208 Actel, AFS250-PQG208 Datasheet - Page 234
AFS250-PQG208
Manufacturer Part Number
AFS250-PQG208
Description
FPGA - Field Programmable Gate Array 250K System Gates
Manufacturer
Actel
Datasheet
1.AFS600-PQG208.pdf
(330 pages)
Specifications of AFS250-PQG208
Processor Series
AFS250
Core
IP Core
Maximum Operating Frequency
1098.9 MHz
Number Of Programmable I/os
93
Data Ram Size
36864
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
250 K
Package / Case
PQFP-208
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Price
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Microsemi SoC
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Device Architecture
Figure 2-137 • Input Register Timing Diagram
Table 2-173 • Input Data Register Propagation Delays
2- 21 8
Data
Enable
Clear
Preset
Out_1
CLK
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
ICLKQ
ISUD
IHD
ISUE
IHE
ICLR2Q
IPRE2Q
IREMCLR
IRECCLR
IREMPRE
IRECPRE
IWCLR
IWPRE
ICKMPWH
ICKMPWL
For the derating values at specific junction temperature and voltage supply levels, refer to
page
Commercial Temperature Range Conditions: T
Input Register
50%
3-9.
Clock-to-Q of the Input Data Register
Data Setup Time for the Input Data Register
Data Hold Time for the Input Data Register
Enable Setup Time for the Input Data Register
Enable Hold Time for the Input Data Register
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width High for the Input Data Register
Clock Minimum Pulse Width Low for the Input Data Register
50%
Timing Characteristics
t
1
ISUE
t
IHE
50%
50%
t
ISUD
0
t
t
ICLKQ
IHD
50%
50%
Description
50%
t
IWPRE
t
IPRE2Q
50%
50%
t
IRECPRE
R e visio n 1
50%
t
ICLR2Q
50%
J
t
IWCLR
= 70°C, Worst-Case VCC = 1.425 V
50%
50%
50%
t
IRECCLR
50%
0.24
0.26
0.00
0.37
0.00
0.45
0.45
0.00
0.22
0.00
0.22
0.22
0.22
0.36
0.32
–2
t
ICKMPWH
t
IREMPRE
50%
0.27
0.30
0.00
0.42
0.00
0.52
0.52
0.00
0.25
0.00
0.25
0.25
0.25
0.41
0.37
–1
50%
t
ICKMPWL
Table 3-7 on
0.32
0.35
0.00
0.50
0.00
0.61
0.61
0.00
0.30
0.00
0.30
0.30
0.30
0.48
0.43
Std.
50%
t
50%
IREMCLR
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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