AFS250-FGG256 Actel, AFS250-FGG256 Datasheet
AFS250-FGG256
Specifications of AFS250-FGG256
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AFS250-FGG256 Summary of contents
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... In Partnership with Pigeon Point Systems • ARM Cortex-M1 Enabled MicroBlade Advanced Mezzanine Card Support (U1) • Targeted to Advanced Mezzanine Card (AdvancedMC Designs) • Designed in Partnership with MicroBlade • 8051-Based Module Management Controller (MMC) AFS090 AFS250 AFS600 M1AFS250 M1AFS600 P1AFS600 U1AFS600 90,000 250,000 600,000 2,304 6,144 ...
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... PQ208 FG256 FG484 FG676 Notes: 1. Fusion devices in the same package are pin compatible with the exception of the PQ208 package (AFS250 and AFS600). 2. MicroBlade devices are only offered in FG256. 3. Pigeon Point devices are only offered in FG484 and FG256 Bank 1 User Nonvolatile Charge Pumps ...
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... Package Type Speed Grade Blank = Standard 1 = 15% Faster than Standard 2 = 25% Faster than Standard Part Number Fusion Devices AFS090 = 90,000 System Gates AFS250 = 250,000 System Gates AFS600 = 600,000 System Gates AFS1500 = 1,500,000 System Gates ARM-Enabled Fusion Devices M1AFS250 = 250,000 System Gates ...
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... Cortex-M1 devices are offered in the same speed grades and packages as basic Fusion devices. • Pigeon Point devices are only offered in –2 speed grade and FG484 and FG256 packages. • MicroBlade devices are only offered in standard speed grade and the FG256 package AFS090 AFS250 M1AFS250 C, I – – – ...
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... QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 180-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 676-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27 Datasheet Information List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 Actel Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 Actel Fusion Family of Mixed Signal FPGAs ...
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... Actel Fusion devices provide an excellent alternative to costly and time-consuming mixed signal ASIC designs. In addition, when used in conjunction with the Actel Cortex-M1, Actel Fusion technology represents the definitive mixed signal FPGA platform ...
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... ADC), enabling a low power standby mode. The Actel Fusion family offers revolutionary features, never before available in an FPGA. The nonvolatile flash technology gives the Fusion solution the advantage of being a secure, low power, single-chip solution that is live at power-up ...
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... Embedded memories – Flash memory blocks – FlashROM – SRAM and FIFO • Clocking resources – PLL and CCC Actel Fusion Family of Mixed Signal FPGAs ...
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... D-flip-flop or latch (with or without enable) by programming the appropriate flash switch interconnections. This versatility allows efficient use of the FPGA fabric. The VersaTile capability is unique to the Actel families of flash-based FPGAs. VersaTiles and larger functions are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming ...
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... FPGA logic or an on-chip soft microprocessor can access flash memory through the parallel interface. Since the flash parallel interface is implemented in the FPGA fabric, it can potentially be customized to meet special user requirements. For more information, refer to the memory parallel interface provides configurable byte-wide (×8), word-wide (×16), or dual-word-wide Actel Fusion Family of Mixed Signal FPGAs R pullup AC ...
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... ECC Logic – The flash memory stores error correction information with each block to perform single-bit error correction and double-bit error detection on all data blocks. User Nonvolatile FlashROM In addition to the flash blocks, Actel Fusion devices have 1 Kbit of user-accessible, nonvolatile FlashROM on-chip. The FlashROM is organized as 8×128-bit pages. The FlashROM can be used in diverse system applications: • ...
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... I/O standards (single-ended and differential). The south bank supports the Analog Quads (analog I/O). In the family's two smaller devices, the north bank supports multiple single-ended digital I/O Actel Fusion Family of Mixed Signal FPGAs ) = 1.5 MHz to 350 MHz ) = 0.75 MHz to 350 MHz ...
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... Double-Data-Rate (DDR) applications—DDR LVDS I/O for chip-to-chip communications • Fusion banks support LVPECL, LVDS, BLVDS, and M-LVDS with 20 multi-drop points. VersaTiles The Fusion core consists of VersaTiles, which are also used in the successful Actel ProASIC3 family. The Fusion VersaTile supports the following: • All 3-input logic functions—LUT-3 equivalent • ...
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... Fusion FPGA Fabric User’s Guide http://www.actel.com/documents/Fusion_UG.pdf Fusion, IGLOO/e and ProASIC3/E Macro Library Guide http://www.actel.com/documents/pa3_libguide_ug.pdf SmartGen, FlashROM, Flash Memory System Builder, and Analog System Builder User's Guide http://www.actel.com/documents/genguide_ug.pdf White Papers Fusion Technology http://www.actel.com/documents/Fusion_Tech_WP.pdf Actel Fusion Family of Mixed Signal FPGAs ...
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... An applet controls or responds to the peripheral(s). Applets can be easily imported or exported from the design environment. The applet structure is open and well-defined, enabling users to import applets from Actel, system developers, third parties, and user groups. ...
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... Device Architecture The system application, Level 3, is the larger user application that utilizes one or more applets. Designing at the highest level of abstraction supported by the Actel Fusion technology stack, the application can be easily created in FPGA gates by importing and configuring multiple applets. In fact, in some cases an entire FPGA system design can be created without any HDL coding. ...
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... Fusion, IGLOO/e and ProASIC3/E Macro Library A OR2 AND2 XOR2 NAND3 C C Figure 2-3 • Sample of Combinatorial Cells Actel Fusion Family of Mixed Signal FPGAs (Figure 2-3). For more details, refer to the Guide. A INV A NOR2 B A NAND2 XOR3 C A MAJ3 0 MUX2 Y B ...
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Device Architecture OUT GND VCCA OUT Figure 2-4 • Combinatorial Timing Model and Waveforms NAND2 or Any Combinatorial Logic MAX(t PD PD(RR) where edges are applicable for the ...
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... 0.70 PD ⊕ 0. 0. 0.56 PD (Figure 2-5). For more details, refer to the Guide Actel Fusion Family of Mixed Signal FPGAs –1 Std. Units 0.46 0.54 ns 0.54 0.63 ns 0.54 0.63 ns 0.55 0.65 ns 0.55 0.65 ns 0.84 0.99 ns 0.79 0.93 ns 1.00 1.17 ns 0.58 0. ...
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Device Architecture Data CLK Data CLK CLR Figure 2-5 • Sample of Sequential Cells 50% CLK 50% Data EN 50 PRE t SUE CLR Out Figure 2-6 • Sequential Timing Model and Waveforms Out Data ...
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... CKMPWH t Clock Minimum Pulse Width Low for the Core Register CKMPWL Note: For the derating values at specific junction temperature and voltage supply levels, refer to page 3-9. Actel Fusion Family of Mixed Signal FPGAs = 70°C, Worst-Case VCC = 1.425 V J Description –2 –1 Std. ...
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... AFS600 device. For more information on how to use array coordinates for region/placement constraints, see the (available in the software) for Fusion software tools. Table 2-3 • Array Coordinates Device VersaTiles Min AFS090 3 2 AFS250 3 2 AFS600 3 4 AFS1500 3 4 Top Row (7, 79) to (189, 79) Bottom Row (5, 78) to (192, 78) (0, 79) ...
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... Input to the core cell for the D-flip-flop set and reset is only available via the VersaNet global network connection. Figure 2-8 • Ultra-Fast Local Lines Connected to the Eight Nearest Neighbors Actel Fusion Family of Mixed Signal FPGAs (Figure 2-8). The exception to this is that the (Figure 2-9 on page 2-10) ...
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Device Architecture Spans Four VersaTiles Figure 2-9 • Efficient Long-Line Resources 2- 10 Spans One VersaTile Spans Two VersaTiles ...
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... High-Speed, Very-Long-Line Resources Pad Ring Figure 2-10 • Very-Long-Line Resources Actel Fusion Family of Mixed Signal FPGAs SRAM 16×12 Block of VersaTiles ...
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Device Architecture Global Resources (VersaNets) Fusion devices offer powerful and flexible control of circuit timing through the use of analog circuitry. Each chip has six CCCs. The west CCC also contains a PLL core. In the two larger devices (AFS600 ...
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... Total Spines VersaTiles in Each Top or Bottom Spine Total VersaTiles Note: *There are six chip (main) globals and three globals per quadrant. Actel Fusion Family of Mixed Signal FPGAs 3 3 Chip (main) Global Network AFS090 AFS250 384 768 2,304 6,144 CCC 3 6 CCC 3 6 ...
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... Signal Figure 2-13 • Spine-Selection MUX of Global Tree 2- 14 (Figure 2-12 on page 2-12). Each spine is accessed by the dedicated global network MUX tree (Figure Using Global Resources in Actel Fusion Internal/External Signals Tree Node MUX Tree Node MUX Global Rib Global Driver MUX ...
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... Global Resources in Actel Fusion Devices Global Spine Global Rib Global Driver and MUX Tree Node MUX Figure 2-14 • Clock Aggregation Tree Architecture Actel Fusion Family of Mixed Signal FPGAs application note. I/O Tiles I/O Access Internal Signal Access Global Signal Access ...
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Device Architecture Global Resource Characteristics AFS600 VersaNet Topology Clock delays are device-specific. global tree presented in is used to drive all D-flip-flops in the device. CCC Figure 2-15 • Example of Global Tree Use in an AFS600 Device for Clock ...
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... Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For the derating values at specific junction temperature and voltage supply levels, refer to Actel Fusion Family of Mixed Signal FPGAs Table 2-5, ...
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... Device Architecture Table 2-7 • AFS250 Global Resource Timing Commercial Temperature Range Conditions: T Parameter Description t Input Low Delay for Global Clock RCKL t Input High Delay for Global Clock RCKH t Maximum Skew for Global Clock RCKSW F Maximum Frequency for Global Clock RMAX Notes: 1 ...
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... The Fusion integrated RC oscillator produces a 100 MHz clock source with no external components. For systems requiring more precise clock signals, the Actel Fusion family supports an on- chip crystal oscillator circuit. The integrated PLLs in each Fusion device can use the RC oscillator, crystal oscillator, or another on-chip clock signal as a source ...
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Device Architecture RC Oscillator The RC oscillator is an on-chip free-running clock source generating a 100 MHz clock. It can be used as a source clock for both on-chip and off-chip resources. When used in conjunction with the Fusion PLL ...
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... XTAL1 and XTAL2, as shown in XT LOSC FPGA_EN* SELMODE MODE[1:0] RTC_MODE[1: Note: *Internal signal—does not exist in macro. Figure 2-17 • XTLOSC Macro Actel Fusion Family of Mixed Signal FPGAs Figure Figure 2-18 for any desired frequency Figure 2-17. XTL_EN* C LKOU T 0 XTL_MODE* ...
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Device Architecture 1.00E-0.3 1.00E-0.4 1.00E-0.5 1.00E-0.6 1.00E-0.7 Figure 2-18 • Crystal Oscillator: RC Time Constant Values vs. Frequency (typical) Table 2-10 • XTLOSC Signals Descriptions Signal Name XTL_EN* XTL_MODE* SELMODE RTC_MODE[1:0] MODE[1:0] FPGA_EN* XTL CLKOUT Note: *Internal signal—does not exist ...
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... This latter mode allows the user to dynamically reconfigure the CCC without the need for core programming. The shift register is accessed through a simple serial interface. Refer to the "UJTAG Applications in Actel’s Low-Power Flash Devices" chapter of the and the " ...
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... INBUF Macro PAD Notes: 1. Visit the Actel website for future application notes concerning dynamic PLL reconfiguration. Refer to the section on page 2-29 for signal descriptions. 2. Many specific INBUF macros support the wide variety of single-ended and differential I/O standards for the Fusion family. ...
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... Fusion devices. The available CLKBUF macros are described in the ProASIC3/E Macro Library Guide. Clock Source CLKBUF_LVDS/LVPECL Macro CLKBUF Macro PADN PAD Y PADP Figure 2-20 • Global Buffers with No Programmable Delay Actel Fusion Family of Mixed Signal FPGAs (Figure 2-20). Clock Conditioning CLKINT Macro None Fusion, IGLOO/e and ...
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Device Architecture Global Buffers with Programmable Delay The CLKDLY macro is a pass-through clock source that does not use the PLL, but provides the ability to delay the clock input using a programmable delay clock input and adds a user-defined ...
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... Do not place a clock source I/O (INBUF or INBUF_LVPECL/LVDS relevant global pin location. 3. LVDS-based clock sources are available in the east and west banks on all Fusion devices. Figure 2-22 • Clock Input Sources Including CLKBUF, CLKBUF_LVDS/LVPECL, and CLKINT Actel Fusion Family of Mixed Signal FPGAs To Core + ...
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Device Architecture CCC Physical Implementation The CCC circuit is composed of the following • PLL core • 3 phase selectors • 6 programmable delays and 1 fixed delay • 5 programmable frequency dividers that provide frequency multiplication/division (not shown in ...
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... GLB, GLC, YB, and YC). SmartGen also allows the user to select where the input clock is coming from. SmartGen automatically instantiates the special macro, PLLINT, when needed. Actel Fusion Family of Mixed Signal FPGAs for more information ...
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Device Architecture CCC and PLL Characteristics Timing Characteristics Table 2-12 • Fusion CCC/PLL Specification Parameter Clock Conditioning Circuitry Input Frequency f Clock Conditioning Circuitry Output Frequency f Delay Increments in Programmable Delay Blocks Number of Programmable Values in Each Programmable ...
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... RC Oscillator W I/O Ring CCC/PLL Clock I/Os From FPGA Core Figure 2-24 • NGMUX Table 2-13 • NGMUX Configuration and Selection Table GLMUXCFG[1:0] GLMUXSEL[1: Actel Fusion Family of Mixed Signal FPGAs GLMUXCFG[1:0] GLINT To Clock Rib Driver PLL/ GLA NGMUX CCC GLC GL PWR UP GLMUXSEL[1:0] ...
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Device Architecture The NGMUX macro is simplified to show the two clock options that have been selected by the GLMUXCFG[1:0] bits. are connected to CLK0 and CLK1 and are controlled by GLMUXSEL[1:0] to determine which signal passed ...
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... Note: *Signals are hardwired internally and do not exist in the macro core. Figure 2-27 • Real-Time Counter System (not all the signals are shown for the AB macro) Actel Fusion Family of Mixed Signal FPGAs Fusion FPGA Fabric User’s Guide shows their connection. ...
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... Note that when VJTAG is not powered, the 1.5 V voltage regulator cannot be enabled through TRST. VPP and VJTAG can control through an external switch. Actel recommends ADG839, ADG849, or ADG841 as possible switches. of the switch can be connected to PTBASE of the Fusion device. VJTAG can be controlled in same manner ...
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... The automatic reset does not apply if the Match Register value is 0x0000000000. The RTCCLK has a prescaler to divide the clock by 128 before it is used for the 40-bit counter. Below is an example of how to calculate the OFF time. Actel Fusion Family of Mixed Signal FPGAs xt_mode[1:0] xtal_en ...
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Device Architecture Example: Calculation for Match Count To put the Fusion device on standby for one hour using an external crystal of 32.768 KHz: The period of the crystal oscillator 32.768 KHz = 30.518 ...
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... RTCPSMMATCH PUB TRST* Note: *Signals are hardwired internally and do not exist in the macro core. Figure 2-30 • VRPSM Macro Actel Fusion Family of Mixed Signal FPGAs Description Use Used to preload the counter to a specified start point. The RTC comparison bits The output of the XNOR gates 0 – ...
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... In Voltage Regulator Initial State Defines the voltage Regulator status upon power-up of the 3.3 V. The signal is configured by Actel Libero (IDE) when the VRPSM macro is generated. Tie off to 1 – Voltage regulator enables when 3 powered. Tie off to 0 – Voltage regulator disables when 3 powered. ...
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... A match value corresponding to the wake-up time is loaded into the Match Register. The 1.5 V voltage regulator is disabled by setting VRPU allow the Fusion device to enter standby mode, when the 1.5 V supply is off but the RTC remains on. Actel Fusion Family of Mixed Signal FPGAs 3 Sleep Mode 3 ...
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... PTBASE and the 1.5 V supplies of the Fusion device. the 1.5 V voltage regulator to an external pass transistor. Actel recommends using a PN2222A or 2N2222A transistor. The gain of such a transistor is approximately 25, with a maximum base current of 20 mA. The maximum current that can be supported is 0.5 A. Transistors with different gain can also be used for different current requirements. ...
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... All flash memory block signals are active high, except for CLK and active low RESET. All flash memory operations are synchronous to the rising edge of CLK. Figure 2-32 • Flash Memory Block Actel Fusion Family of Mixed Signal FPGAs Figure 2-32. The port pin name and descriptions are detailed ...
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Device Architecture Flash Memory Block Pin Names Table 2-19 • Flash Memory Block Pin Names Interface Name Width Direction ADDR[17:0] 18 AUXBLOCK 1 BUSY 1 CLK 1 DATAWIDTH[1:0] 2 DISCARDPAGE 1 ERASEPAGE 1 LOCKREQUEST 1 OVERWRITEPAGE 1 OVERWRITEPROTECT 1 PAGESTATUS ...
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... Erase-Page/Program: page write count has exceeded the 10-year retention threshold In When asserted, the page addressed is copied into the Page Buffer and the Page Buffer is made writable. In Write data In When asserted, stores WD in the page buffer Actel Fusion Family of Mixed Signal FPGAs 2- 43 ...
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Device Architecture Flash Memory Block Diagram A simplified diagram of the flash memory block is shown in Output RD[31:0] MUX WD[31 :0] ADDDR[17:0] DATAWIDTH[1:0] REN READNEXT PAGESTATUS WEN ERASEPAGE PROGRAM SPAREPAGE Control AUXBLOCK Logic UNPROTECTPAGE OVERWRITEPAGE DISCARDPAGE OVERWRITEPROTECT PAGELOSSPROTECT PIPE ...
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... When the Auxiliary block is addressed (AUXBLOCK active), ADDR[6:2] are ignored. Note: The spare page of sector 0 is unavailable for any user data. Writes to this page will return an error, and reads will return all zeroes. Actel Fusion Family of Mixed Signal FPGAs Spare Page Page 31 ...
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Device Architecture Data operations are performed in widths bytes. A write to a location in a page that is not already in the Page Buffer will cause the page to be read from the FB Array ...
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... Write errors include the following: 1. Attempting to write a page that is Overwrite Protected (STATUS = '01'). The write is not performed. 2. Attempting to write to a page that is not in the Page Buffer when Page Loss Protection is enabled (STATUS = '11'). The write is not performed. Actel Fusion Family of Mixed Signal FPGAs Figure 2-35 on page 2- ...
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Device Architecture Program Operation A Program operation is initiated by asserting the PROGRAM signal on the interface. Program operations save the contents of the Page Buffer to the FB Array. Due to the technologies inherent in the FB, a program ...
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... The ECC Logic determining that there is an uncorrectable error within the erased page (STATUS = '10') CLK ERASE ADDR[17:0] Page OVERWRITEPROTECT PAGELOSSPROTECT BUSY STATUS[1:0] Figure 2-37 • FB Erase Page Waveform Actel Fusion Family of Mixed Signal FPGAs Figure 2-37 Valid 2- 49 ...
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Device Architecture Read Operation Read operations are designed to read data from the FB Array, Page Buffer, Block Buffer, or status registers. Read operations support a normal read and a read-ahead mode (done by asserting READNEXT). Also, the timing for ...
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... JTAG operations. This bit can be overridden by using the correct user key value. 0 Overwrite Protected; designates that the user has set the OVERWRITEPROTECT bit on the interface while doing a Program operation. The page cannot be written without first performing an Unprotect Page operation. Actel Fusion Family of Mixed Signal FPGAs Table 2-24 Read Protected ...
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Device Architecture Read Next Operation The Read Next operation is a feature by which the next block relative to the block in the Block Buffer is read from the FB Array while performing reads from the Block Buffer. The goal ...
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... This command results in the Page Buffer being marked as unmodified. The timing for the operation is shown in operation has completed. CLK DISCARDPAGE BUSY Figure 2-43 • FB Discard Page Waveform Actel Fusion Family of Mixed Signal FPGAs Figure 2-42. Figure 2-43. The BUSY signal will remain asserted until the Valid ...
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Device Architecture Flash Memory Block Characteristics CLK RESET Active Low, Asynchronous BUSY Figure 2-44 • Reset Timing Diagram Table 2-25 • Flash Memory Block Timing Commercial Temperature Range Conditions: T Parameter t Clock-to-Q in 5-cycle read mode of the Read ...
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... Clock Minimum Pulse Width for the Control Logic MPWCLKNVM t Maximum Frequency for Clock for the Control Logic – for FMAXCLKNVM AFS1500/AFS600 Maximum Frequency for Clock for the Control Logic – for AFS250/AFS090 Actel Fusion Family of Mixed Signal FPGAs = 70°C, Worst-Case VCC = 1.425 V J Description 1.69 0.00 2 ...
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Device Architecture FlashROM Fusion devices have 1 kbit of on-chip nonvolatile flash memory that can be read from the FPGA core fabric. The FlashROM is arranged in eight banks of 128 bits during programming. The 128 bits in each bank ...
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... Table 2-26 • FlashROM Access Time Commercial Temperature Range Conditions: T Parameter Description t Address Setup Time SU t Address Hold Time HOLD t Clock to Out CK2Q F Maximum Clock frequency MAX Actel Fusion Family of Mixed Signal FPGAs HOLD HOLD A1 t CK2Q D0 = 70°C, Worst-Case VCC = 1.425 V J –2 – ...
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Device Architecture SRAM and FIFO All Fusion devices have SRAM blocks along the north side of the device. Additionally, AFS600 and AFS1500 devices have an SRAM block on the south side of the device. To meet the needs of high- ...
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... WCLK FREN FWEN CNT 12 RBLK REN E ESTOP CNT 12 WBLK WEN E FSTOP Reset Figure 2-47 • Fusion RAM Block with Embedded FIFO Controller Actel Fusion Family of Mixed Signal FPGAs WD[17:0] RCLK WCLK RAM RADD[J:0] WADD[J:0] REN WEN = FULL AFVAL AFULL AEVAL AEMPTY ...
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Device Architecture RAM4K9 Description Figure 2-48 • RAM4K9 2- 60 RAM4K9 ADDRA11 DOUTA8 DOUTA7 ADDRA10 DOUTA0 ADDRA0 DINA8 DINA7 DINA0 WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA ADDRB11 DOUTB8 ADDRB10 DOUTB7 ADDRB0 DOUTB0 DINB8 DINB7 DINB0 WIDTHB1 WIDTHB0 PIPEB WMODEB ...
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... Table 2-28 • Address Pins Unused/Used for Various Supported Bus Widths D×W Unused 4k×1 2k×2 1k×4 512×9 Note: The "x" in ADDRx implies Actel Fusion Family of Mixed Signal FPGAs WIDTHB1, WIDTHB0 (Table 2-28). ADDRx None ...
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Device Architecture DINA and DINB These are the input data signals, and they are nine bits wide. Not all nine bits are valid in all configurations. When a data width less than nine is specified, unused high-order signals must be ...
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... RAM512X18 Description Figure 2-49 • RAM512X18 Actel Fusion Family of Mixed Signal FPGAs RAM512X18 RADDR8 RD17 RADDR7 RD16 RADDR0 RD0 RW1 RW0 PIPE REN RCLK WADDR8 WADDR7 WADDR0 WD17 WD16 WD0 WW1 WW0 WEN WCLK RESET ...
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Device Architecture RAM512X18 exhibits slightly different behavior from RAM4K9 has dedicated read and write ports. WW and RW These signals enable the RAM to be configured in one of the two allowable aspect ratios Table 2-30 • Aspect ...
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... The shift register for a target block can be selected and loaded with the proper Blocks bit configuration to enable serial loading. The 4,608 bits of data can be loaded in a single operation. Actel Fusion Family of Mixed Signal FPGAs "SRAM Characteristics" section on page 2-66 2-77. ...
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Device Architecture SRAM Characteristics Timing Waveforms CLK t AS ADD t BKS BLK_B t ENS WEN_B Figure 2-50 • RAM Read for Flow-Through Output CLK t AS ADD t BKS BLK_B t ENS WEN_B DO Figure 2-51 ...
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... ENS WEN_B Figure 2-52 • RAM Write, Output Retained (WMODE = 0) t CKH CLK ADD 0 t BKS BLK_B t ENS WEN_B (flow-through) DO (pipelined) Figure 2-53 • RAM Write, Output as Write Data (WMODE = 1) Actel Fusion Family of Mixed Signal FPGAs t CKL ENH CYC t CKL BKH ...
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Device Architecture CLK1 ADD1 DI1 CLK2 ADD2 DO2 (flow-through) DO2 (Pipelined) Figure 2-54 • One Port Write / Other Port Read Same CLK1 t AS ADD1 t DI1 CLK2 WEN_B1 WEN_B2 ADD2 DI2 DO2 (pass-through) DO2 (pipelined) Figure 2-55 • ...
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... CLK1 ADD1 DI1 WRO CLK2 WEN_B1 WEN_B2 ADD2 CKQ1 DO2 D n (pass-through) DO2 D (pipelined) n Figure 2-56 • Read Access After Write onto Same Address Actel Fusion Family of Mixed Signal FPGAs CKQ2 ...
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Device Architecture CLK1 ADD1 WEN_B1 DO1 D (pass-through) DO1 (pipelined) CLK2 ADD2 DI2 WEN_B2 Figure 2-57 • Write Access After Read onto Same Address CLK RESET_B Figure 2-58 • RAM Reset ...
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... Clock cycle time CYC F Maximum frequency MAX Note: For the derating values at specific junction temperature and voltage supply levels, refer to page 3-9. Actel Fusion Family of Mixed Signal FPGAs = 70°C, Worst-Case VCC = 1.425 V J Description –2 –1 Std. Units 0.25 0.28 0. ...
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Device Architecture Table 2-32 • RAM512X18 Commercial Temperature Range Conditions: T Parameter t Address setup time AS t Address hold time AH t REN_B, WEN_B setup time ENS t REN_B, WEN_B hold time ENH t Input data (DI) setup time ...
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... FIFO4K18 Description Figure 2-59 • FIFO4KX18 Actel Fusion Family of Mixed Signal FPGAs FIFO4K18 RW2 RD17 RD16 RW1 RW0 WW2 WW1 RD0 WW0 ESTOP FULL FSTOP AFULL EMPTY AEVAL11 AEMPTY AEVAL10 AEVAL0 AFVAL11 AFVAL10 AFVAL0 REN RBLK RCLK WD17 WD16 WD0 WEN ...
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Device Architecture The following signals are used to configure the FIFO4K18 memory element: WW and RW These signals enable the FIFO to be configured in one of the five allowable aspect ratios Table 2-33 • Aspect Ratio Settings for WW[2:0] ...
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... ESTOP, where the read counter keeps counting, would be writing to the FIFO once and reading the same content over and over without doing another write. Actel Fusion Family of Mixed Signal FPGAs "ESTOP and FSTOP Usage" section on page "FIFO Flag Usage Considerations" section 2-75 ...
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Device Architecture FIFO Flag Usage Considerations The AEVAL and AFVAL pins are used to specify the 12-bit AEMPTY and AFULL threshold values, respectively. The FIFO contains separate 12-bit write address (WADDR) and read address (RADDR) counters. WADDR is incremented every ...
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... AEF t RSTFG FF AFF WA/RA (Address Counter) Figure 2-60 • FIFO Reset RCLK EF AEF WA/RA NO MATCH (Address Counter) Figure 2-61 • FIFO EMPTY Flag and AEMPTY Flag Assertion Actel Fusion Family of Mixed Signal FPGAs t MPWRSTB t RSTAF t RSTAF MATCH ( CYC t CKAF NO MATCH Dist = AEF_TH ...
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Device Architecture WCLK FF AFF WA/RA NO MATCH (Address Counter) Figure 2-62 • FIFO FULL and AFULL Flag Assertion WCLK WA/RA MATCH NO MATCH (EMPTY) (Address Counter) 1st rising edge after 1st write RCLK EF AEF Figure 2-63 • FIFO ...
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... Actel Fusion Family of Mixed Signal FPGAs –1 Std. Units 1.52 1.79 ns 0.00 0.00 ns 0.22 0.26 ns 0.00 0.00 ns 0.21 0.25 ns 0.00 0. ...
Page 96
... By supporting higher internal voltages, the Actel advanced flash process enables high dynamic range on analog circuitry, increasing precision and signal–noise ratio. Actel flash FPGAs also drive high-voltage outputs, eliminating the need for external level shifters and drivers. ...
Page 97
... STC[7:0] CHNUMBER[4:0] TMSTINT ADCSTART VAREFSEL PWRDWN ADCRESET RTCCLK SYSCLK ACMWEN ACMRESET ACMWDATA ACMADDR ACMCLK Figure 2-65 • Analog Block Macro Actel Fusion Family of Mixed Signal FPGAs DAVOUT0 DACOUT0 DATOUT0 DAVOUT9 DACOUT9 DATOUT9 AG0 AG1 AG9 BUSY CALIBRATE DATAVALID SAMPLE RESULT[11:0] RTCMATCH ...
Page 98
... When asserted, the ADC will stop functioning, and the digital portion of the analog operating. This may result in invalid status flags from the analog block. Therefore, Actel does not recommend asserting the PWRDWN pin. 1 Input ADC resets and disables Analog Quad – active high 1 Output 1 – ...
Page 99
... AT3 AV4 AC4 AG4 AT4 ATRETURN45 AV5 AC5 AG5 AT5 AV6 AC6 Actel Fusion Family of Mixed Signal FPGAs Direction Function 10 Input Control to power MOS – 1 per quad 10 Input Temperature monitor strobe – 1 per quad; active high 30 Output Digital outputs – 3 per quad ...
Page 100
... RTCXTLSEL RTCCLK Analog Quad With the Fusion family, Actel introduces the Analog Quad, shown in basic analog I/O structure. The Analog Quad is a four-channel system used to precondition a set of analog signals before sending it to the ADC for conversion into a digital signal. To maximize the usefulness of the Analog Quad, the analog input signals can also be configured as LVTTL digital input signals ...
Page 101
... It has a modified prescaler and is limited to positive voltages only. The Analog Quad can be configured during design time by Actel Libero IDE; however, the ACM can be used to change the parameters of any of these I/Os during runtime. This type of change is referred context switch ...
Page 102
Device Architecture Voltage Monitor The Fusion Analog Quad offers a robust set of voltage-monitoring capabilities unique in the FPGA industry. The Analog Quad comprises three analog input pads— Analog Voltage (AV), Analog Current (AC), and Analog Temperature (AT)—and a single ...
Page 103
... To FPGA (DAVOUTx) To Analog MUX Figure 2-68 • Analog Quad Prescaler Input Configuration Actel Fusion Family of Mixed Signal FPGAs is ON) or when the resource is not used, analog inputs are pulled down to Table 2-54 on page 2-132, and the gain error (which contributes to the Table 2-46 on page 2-119 ...
Page 104
Device Architecture Terminology BW – Bandwidth range of frequencies that a Channel can handle. Channel A channel is define as an analog input configured as one of the Prescaler range shown in page 2-132. The channel includes ...
Page 105
... AV Voltage Pads Monitor Block On-Chip Prescaler Digital Input To FPGA (DAVOUTx) To Analog MUX Figure 2-70 • Analog Quad Direct Digital Input Configuration Actel Fusion Family of Mixed Signal FPGAs AC AG Current Gate Monitor Block Driver Analog Quad Prescaler Power MOSFET Digital Gate Driver ...
Page 106
Device Architecture Current Monitor The Fusion Analog Quad is an excellent element for voltage- and current-monitoring applications. In addition to supporting the same functionality offered by the AV pad, the AC pad can be configured to monitor current across an ...
Page 107
... ADC is the result from the ADC VAREF is the Reference voltage N is the number of bits Rsense is the resistance of the sense resistor Actel Fusion Family of Mixed Signal FPGAs in order to discharge the previous measurement. Then CMSLO prior to asserting the ADCSTART signal. The CMSTB CMSET ...
Page 108
Device Architecture 0-12 V AVx Current Monitor Figure 2-73 • Positive Current Monitor Care must be taken when choosing the right resistor for current measurement application. Note that because of the 10× amplification, the maximum measurable difference between the AV ...
Page 109
... N is the number of bits is the Reference voltage V AREF is the voltage at AV pad the voltage at AC pad V AC Actel Fusion Family of Mixed Signal FPGAs Recommended Minimum Resistor Value (Ohms) 10 – – 10 2.5 – – 2 0.5 – 1 0.3 – 0.5 0.1 – 0.2 0.05 – 0.1 0.025 – ...
Page 110
Device Architecture Gate Driver The Fusion Analog Quad includes a Gate Driver connected to the Quad's AG pin Designed to work with external p- or n-channel MOSFETs, the Gate driver is a configurable current sink or source and requires an ...
Page 111
... Thus, used for a first-order estimate of the switching speed of the external MOSFET. 1 μA 3 μ μA 3 μA Figure 2-76 • Gate Driver Example Actel Fusion Family of Mixed Signal FPGAs page 2-94 High Current 10 μA 30 μA High Current 10 μ ...
Page 112
Device Architecture Temperature Monitor The final pin in the Analog Quad is the Analog Temperature (AT) pin. The AT pin is used to implement an accurate temperature monitor in conjunction with an external diode-connected bipolar transistor (Figure 2-77). For improved ...
Page 113
... Temperature Monitor cannot be less than the minimum strobe high time minus the setup time. Figure 2-79 shows the timing diagram. TMSTBx t TMSLO VADC ADCSTART Figure 2-79 • Timing Diagram for the Temperature Monitor Strobe Signal Actel Fusion Family of Mixed Signal FPGAs VDD33A + + VADC 12.5 X ∆V – – t ...
Page 114
... Temperature Strobe is High, typically 10 µA I TMSHI is diode voltage while Temperature Strobe is Low V TMSLO is diode voltage while Temperature Strobe is High V TMSHI n is the non-ideality factor of the diode-connected transistor typically 1.004 for the Actel- recommended transistor type 2N3904. - 1.3806 1.602 x 10 When TMSLO TMSHI In the Fusion TMB, the ideality factor n for 2N3904 is 1.004 and Δ ...
Page 115
... All results are MSB-justified in the ADC. The input to the ADC is a large 32:1 analog input multiplexer. A simplified block diagram of the Analog Quads, analog input multiplexer, and ADC is shown in Figure 2-80. The ADC offers multiple self-calibrating modes to ensure consistent high performance both at power-up and during runtime. Actel Fusion Family of Mixed Signal FPGAs ...
Page 116
Device Architecture Pads AV0 AC0 Analog AG0 AT0 Quad 0 ATRETURN01 AV1 Analog AC1 AG1 Quad 1 AT1 AV2 AC2 Analog AG2 Quad 2 AT2 ATRETURN23 AV3 Analog AC3 Quad 3 AG3 AT3 AV4 AC4 Analog AG4 AT4 Quad 4 ...
Page 117
... Actel Fusion Family of Mixed Signal FPGAs "Analog Quad" section on page 2-84). "Fusion Family" table on page I and the internal temperature diode remain on Channels 0 CC 2-102. Table 2-39 shows the correlation between the Signal Analog Quad Number Vcc_analog AV0 Analog Quad 0 AC0 AT0 ...
Page 118
Device Architecture Table 2-39 • Analog MUX Channels (continued) Analog MUX Channel Table 2-40 • Channel Selection Channel Number ...
Page 119
... ADC Description The Actel Fusion ADC is a 12-bit SAR ADC. It offers a wide variety of features for different use models. Figure 2-81 shows a block diagram of the Fusion ADC. • Configurable resolution: 8-bit, 10-bit, and 12-bit mode • DNL: 0.6 LSB for 10-bit mode • ...
Page 120
Device Architecture ADC Configuration Description The Fusion ADC can be configured to operate in 8-, 10-, or 12-bit modes, power-down after conversion, and dynamic calibration. This is controlled by MODE[3:0], as defined in The output of the ADC is the ...
Page 121
... If the post-calibration phase is skipped, then the BUSY signal goes to '0' after distribution phase. As soon as BUSY signal goes to '0', the DATAVALID signal goes to '1', indicating the digital result is available on the RESULT output signals. DATAVAILD will remain '1' until the next ADCSTART is asserted. Actel recommends enabling post-calibration to compensate for drift and temperature-dependent effects. This ensures that the ADC remains consistent over time and with temperature ...
Page 122
... From Table 2-47 on page calculation will first compute the post-calibration time, second the distribution time, and finally the STC setting. Since Actel recommends post-calibration for temperature drift over time, post-calibration shall be enabled and the post-calibration time, t 0.24 µs. The distribution time, t ...
Page 123
... Since the ADC is synchronous, the minimum time to issue a second conversion is two clock cycles of SYSCLK after the previous one. (conversion that starts during the power-up calibration). The total time for calibration still remains 3,840 ADCCLK cycles. Actel Fusion Family of Mixed Signal FPGAs Figure 2-82 on page 2-108. In this mode, the (Figure 2-84 on page Figure 2-83 on page 2-108 ...
Page 124
Device Architecture Timing Diagram SYSCLK t RECCLR ADCRESET TVC[7:0] CALIBRATE Note: *Refer page 2-104 Figure 2-82 • Power-Up Calibration Status Signal Timing Diagram SYSCLK ADCSTART MODE[3:0] TVC[7:0] STC[7:0] VAREF CHNUMBER[7:0] Figure 2-83 • Input Setup Time ...
Page 125
... ADCSTART 1st Conversion BUSY t CK2QSAMPLE SAMPLE t CK2QVAL DATAVALID Note: *t represents the conversion time of the second conversion. See CONV conversion time CONV Figure 2-85 • Intra-Conversion Timing Diagram Actel Fusion Family of Mixed Signal FPGAs t t SAMPLE 1 DATA2START t HDADCSTART t CK2QBUSY t CK2QSAMPLE CONV CK2QVAL t ...
Page 126
Device Architecture SYSCLK ADCRESET ADCSTART BUSY SAMPLE t CLR2QVAL DATAVALID t CK2QCAL CALIBRATE Interrupts Power-Up Calibration Note: * See page 2-98 Figure 2-86 • Injected-Conversion Timing Diagram CK2QBUSY t t CK2QSAMPLE CK2QSAMPLE t ...
Page 127
... Recovery Time of Clear RECCLR t Removal Time of Clear REMCLR t Clock Minimum Pulse Width for the ADC MPWSYSCLK t Clock Maximum Frequency for the ADC FMAXSYSCLK Actel Fusion Family of Mixed Signal FPGAs = 70°C, Worst-Case VCC = 1.425 V J Description –2 0.56 0.26 0.68 0.32 1.58 1.27 ...
Page 128
Device Architecture Terminology Conversion Time Conversion time is the interval between the release of the hold state (imposed by the input circuitry of a track-and-hold) and the instant at which the voltage on the sampling capacitor settles to within one ...
Page 129
... Figure 2-88 • Gain Error Gain Error Drift Gain-error drift is the variation in gain error due to a change in ambient temperature, typically expressed in ppm/°C. Actel Fusion Family of Mixed Signal FPGAs (Figure 2-88). Gain = 2 LSB Ideal Output Actual Output Input Voltage to Prescaler ...
Page 130
Device Architecture INL – Integral Non-Linearity INL is the deviation of an actual transfer function from a straight line. After nullifying offset and gain errors, the straight line is either a best-fit straight line or a line drawn between the ...
Page 131
... THD measures the distortion content of a signal, and is specified in decibels relative to the carrier (dBc). THD is the ratio of the RMS sum of the selected harmonics of the input signal to the fundamental itself. Only harmonics within the Nyquist limit are included in the measurement. Actel Fusion Family of Mixed Signal FPGAs Ideal Output Actual Output Offset Error = 1 ...
Page 132
Device Architecture TUE – Total Unadjusted Error TUE is a comprehensive specification that includes linearity errors, gain error, and offset error the worst-case deviation from the ideal device performance. TUE is a static specification Figure 2-91 • Total ...
Page 133
... Temperature Errror vs. Die Temperature 3.5 3 2.5 2 1.5 1 0.5 0 –40 Figure 2-92 • Temperature Error Temperature Error vs. Interconnect Capacitance 500 Figure 2-93 • Effect of External Sensor Capacitance Actel Fusion Family of Mixed Signal FPGAs 10 60 110 Temperature (°C) 1000 1500 Capacitance ( 2000 2- 117 ...
Page 134
Device Architecture Figure 2-94 • Temperature Reading Noise When Averaging is Used Temperature Reading Noise RMS vs. Averaging 1 10 100 Number of Averages R e visio n 1 1000 ...
Page 135
... When using SmartGen Analog System Builder, CalibIP is required to obtain 0 offset. For further details on CalibIP, refer to the "Temperature, Voltage, and Current Calibration in Fusion FPGAs" chapter of the Guide. Actel Fusion Family of Mixed Signal FPGAs = 85°C (unless noted otherwise), J Condition Min. ...
Page 136
... ADC AFS090, AFS250 AFS600, AFS1500 7 uncalibrated 7 AFS600, AFS1500 calibrated High level, TMSTBx = 0 Low level, TMSTBx = 1 8-bit ADC 4 10-bit ADC 1 12-bit ADC 0.25 AFS090, AFS250 5 AFS600, AFS1500 11 7 uncalibrated 7 AFS600, AFS1500 calibrated does not exceed these limits. IND R e visio n 1 Typ. ...
Page 137
... When using SmartGen Analog System Builder, CalibIP is required to obtain 0 offset. For further details on CalibIP, refer to the "Temperature, Voltage, and Current Calibration in Fusion FPGAs" chapter of the Guide. Actel Fusion Family of Mixed Signal FPGAs = 85°C (unless noted otherwise), J Condition Min. ...
Page 138
Device Architecture Table 2-47 • ADC Characteristics in Direct Input Mode Commercial Temperature Range Conditions, T Typical: VCC33A = 3.3 V, VCC = 1.5 V Parameter Description Direct Input using Analog Pad AV, AC Input Voltage (Direct Input) ...
Page 139
... Conversion Rate Conversion Time Sample Rate Notes: 1. Accuracy of the external reference is 2.56 V ± 4.6 mV. 2. Data is based on characterization. 3. The sample rate is time-shared among active analog inputs. Actel Fusion Family of Mixed Signal FPGAs = 85°C (unless noted otherwise), J Condition Min. Typ. 8-bit mode 48 ...
Page 140
Device Architecture Table 2-48 • Uncalibrated Analog Channel Accuracy* Worst-Case Industrial Conditions, T Total Channel Error (LSB) Analog Prescaler Neg. Pad Range (V) Max. Med. Positive Range AV –22 –2 8 –40 –5 4 –45 –9 2 –70 ...
Page 141
... Requires enabling Analog Calibration using SmartGen Analog System Builder. For further details, refer to the "Temperature, Voltage, and Current Calibration in Fusion FPGAs" chapter of the 3. Calibrated with two-point calibration methodology, using 20% and 80% full-scale points. 4. The lower limit of the input voltage is determined by the prescaler input offset. Actel Fusion Family of Mixed Signal FPGAs 1,2,3 = 85°C J ...
Page 142
Device Architecture Table 2-50 • Analog Channel Accuracy: Monitoring Standard Positive Voltages Typical Conditions, T Calibrated Typical Error per Positive Prescaler Setting Input Voltage 16 V ( (AT) (AV/AC ...
Page 143
... Equivalent voltage per LSB = 8 mV for prescaler, with ADC in 10-bit mode LSB Count = ± (5.0 V × 1%) / (0.008) LSB Count = ± 6.25 The 8 V prescaler satisfies the calculated LSB count accuracy requirement (see page 2-125). Actel Fusion Family of Mixed Signal FPGAs Table 2- 127 ...
Page 144
... The ACM is the interface between the FPGA, the Analog Block configurations, and the real-time counter. Actel Libero IDE will generate IP that will load and configure the Analog Block via the ACM. However, users are not limited to using the Libero IDE IP. This section provides a detailed description of the ACM's register map, truth tables for proper configuration of the Analog Block and RTC, as well as timing waveforms so users can access and control the ACM directly from their designs ...
Page 145
... ACMRDATA Figure 2-96 • ACM Read Waveform 1. When addressing the RTC addresses (i.e., ACMADDR 64 to 89), there is no timing generator, and the rc_osc, byte_en, and aq_wen signals have no impact. Actel Fusion Family of Mixed Signal FPGAs Name Description MATCHREG1 Match register bits 15:8 ...
Page 146
Device Architecture Timing Characteristics Table 2-52 • Analog Configuration Multiplexer (ACM) Timing Commercial Temperature Range Conditions: T Parameter t Clock-to-Q of the ACM CLKQACM t Data Setup time for the ACM SUDACM t Data Hold time for the ACM HDACM ...
Page 147
... Selects G-pad polarity Selects low/high drive Scaling factor control – prescaler Analog MUX select Direct analog input switch – Prescaler op amp mode Actel Fusion Family of Mixed Signal FPGAs Default Setting Highest voltage range Prescaler Off Off Positive Power-down Highest voltage range ...
Page 148
Device Architecture Table 2-54 details the settings available to control the prescaler values of the AV, AC, and AT pins. Note that the AT pin has a reduced number of available prescaler values. Table 2-54 • Prescaler Control Truth Table—AV ...
Page 149
... Table 2-63 details the settings available to turn on and off the chip internal temperature monitor. Table 2-63 • Internal Temperature Monitor Control Truth Table Control Lines B2[ Actel Fusion Family of Mixed Signal FPGAs Prescaler Op Amp Power-down Operational Current Monitor Input Switch Off On Control Lines B2[2] ...
Page 150
... I/O Banks and I/O Standards Compatibility The digital I/Os are grouped into I/O voltage banks. There are three digital I/O banks on the AFS090 and AFS250 devices and four digital I/O banks on the AFS600 and AFS1500 devices. page 2-160 and Figure 2-112 on page 2-161 the I/O in the AFS600 and AFS1500 devices comprises two banks of Actel Pro I/Os ...
Page 151
... LVCMOS 2.5/5.0 V, 3.3 V PCI / 3.3 V PCI-X Pro I/O LVTTL/LVCMOS 3.3 V, LVCMOS 2 1 1.5 V, LVCMOS 2.5/5.0 V, 3.3 V PCI / 3.3 V PCI-X Actel Fusion Family of Mixed Signal FPGAs CCC Up to five VREF minibanks within an I/O bank Common VREF signal for all I/Os in VREF minibanks ...
Page 152
... SSTL3 (Class I and II) 1.25 V SSTL2 (Class I and II) 1.0 V GTL+ 2.5, GTL+ 3.3 0.8 V GTL 2.5, GTL 3.3 0.75 V HSTL (Class I), HSTL (Class II) Note: *I/O standards supported by Pro I/O banks AFS250 – – Compatible Standards Compatible Standards R e visio n 1 AFS600 AFS1500 – ...
Page 153
... Table 2-68 • Fusion Standard and Advanced I/O Features 3.3 V – 0.80 V 1.00 V 1.50 V 2.5 V – 0.80 V 1.00 V 1.25 V 1.8 V – 1.5 V – 0.75 V Note: White box: Allowable I/O standard combinations Gray box: Illegal I/O standard combinations Actel Fusion Family of Mixed Signal FPGAs 137 ...
Page 154
Device Architecture Features Supported on Pro I/Os Table 2-69 lists all features supported by transmitter/receiver for single-ended and differential I/Os. Table 2-69 • Fusion Pro I/O Features Feature Single-ended and voltage- referenced transmitter features Single-ended receiver features Voltage-referenced differential receiver ...
Page 155
... HSTL-II SSTL2-I SSTL2-II SSTL3-I SSTL3-II GTL+ 3.3 V GTL+ 2.5 V GTL 3.3 V GTL 2.5 V LVDS LVPECL Actel Fusion Family of Mixed Signal FPGAs Performance Up To 200 MHz 250 MHz 200 MHz 130 MHz 200 MHz 200 MHz 300 MHz 300 MHz 300 MHz ...
Page 156
Device Architecture I/O Registers Each I/O module contains several input, output, and enable registers. Refer to simplified representation of the I/O block. The number of input registers is selected by a set of switches (not shown in registers to implement ...
Page 157
... INBUF B CLK CLKBUF C CLR INBUF Figure 2-99 • DDR Input Register Support in Fusion Devices Actel Fusion Family of Mixed Signal FPGAs Figure 2-99. Three input registers are used to Figure 2-100 on page 2-142. New data is presented to the for more information. Input DDR D Out_QF ...
Page 158
Device Architecture Data_F (from core) CLK CLKBUF Data_R (from core) CLR INBUF Figure 2-100 • DDR Output Support in Fusion Devices FF1 FF2 B C DDR_OUT R e visio n 1 ...
Page 159
... Yes Bus may an active have active bus I/O processes ongoing, but device being inserted or removed must be idle. Actel Fusion Family of Mixed Signal FPGAs Device Example of Card Circuitry Application with Ground Connected Cards that Contain Connection to Bus Pins Fusion Devices – – ...
Page 160
Device Architecture For Fusion devices requiring Level 3 and/or Level 4 compliance, the board drivers connected to Fusion I/Os need to have 10 kΩ (or lower) output drive resistance at hot insertion, and 1 kΩ (or lower) output drive resistance ...
Page 161
... Insertion Tolerance No Yes Yes Yes No Yes No Yes No Yes No Yes No Yes No No Yes No No Yes Yes Actel Fusion Family of Mixed Signal FPGAs Table 2-72 and 1 Advanced Input Output I/O Buffer Buffer 1 1 Yes Enabled/Disabled 1 Yes Enabled/Disabled No Enabled/Disabled 2 Yes Enabled/Disabled No Enabled/Disabled No Enabled/Disabled No Enabled/Disabled ...
Page 162
Device Architecture 5 V Input Tolerance I/Os can support 5 V input tolerance when LVTTL 3.3 V, LVCMOS 3.3 V, LVCMOS 2 and LVCMOS 2.5 V configurations are used (see recommended solutions (see setups) to achieve ...
Page 163
... Off-Chip 5.5 V Rext1 Zener 3.3 V Requires one board resistor, one Zener 3.3 V diode, LVCMOS 3.3 V I/Os Figure 2-102 • Solution 2 Actel Fusion Family of Mixed Signal FPGAs Table 3-4 on page 3-4. Solution 1 Fusion I/O Input On-Chip 3.3 V Rext2 Requires two board resistors, LVCMOS 3 ...
Page 164
Device Architecture Solution 3 The board-level design must ensure that the reflected waveform at the pad does not exceed limits provided in Table 3-4 on page This scheme will also work for a 3.3 V PCI/PCIX configuration, but the internal ...
Page 165
... 420 Ω 100°C J Notes: 1. Speed and current consumption increase as the board resistance values decrease. 2. Resistor values ensure I/O diode long-term reliability. Actel Fusion Family of Mixed Signal FPGAs Speed Current Limitations 1 Low to high Limited by transmitter's drive strength Medium Limited by transmitter's drive strength ...
Page 166
Device Architecture 5 V Output Tolerance Fusion I/Os must be set to 3.3 V LVTTL or 3.3 V LVCMOS mode to reliably drive 5 V TTL receivers also critical that there be NO external I/O pull-up resistor to ...
Page 167
... Figure 2-106 • Timing Diagram (option1: bypasses skew circuit) ENABLE (IN) ENABLE (OUT) 1.2 ns (typical) Figure 2-107 • Timing Diagram (option 2: enables skew circuit) Actel Fusion Family of Mixed Signal FPGAs ENABLE (OUT) MUX Skew Select Less than 0.1 ns Less than 0.1 ns ...
Page 168
Device Architecture At the system level, the skew circuit can be used in applications where transmission activities on bidirectional data lines need to be coordinated. This circuit, when selected, provides a timing margin that can prevent bus contention and subsequent ...
Page 169
... Table 2-80 on page 2-157 lists the default values for the above selectable I/O attributes as well as those that are preset for each I/O standard. Actel Fusion Family of Mixed Signal FPGAs Transmitter 1: OFF Transmitter 1: ON Transmitter 2: OFF of its corresponding I/O bank. When it is pulled down for more information ...
Page 170
Device Architecture Refer to Table 2-75, Table 2-78 on page 2-155 page 2-157 lists the voltages for the supported I/O standards. Table 2-75 • Fusion Standard I/O Standards—OUT_DRIVE Settings I/O Standards LVTTL/LVCMOS 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V ...
Page 171
... GTL (3.3 V) GTL (2.5 V) HSTL Class I HSTL Class II SSTL2 Class I and II SSTL3 Class I and II LVDS, BLVDS, M-LVDS LVPECL Actel Fusion Family of Mixed Signal FPGAs OUT_DRIVE (output only) Refer to the following Off None tables for more information: Off None Table 2-75 on page 2-154 ...
Page 172
Device Architecture Table 2-79 • Advanced I/O Default Attributes I/O Standards SLEW (output only) LVTTL/LVCMOS 3.3 V Refer to the following tables for more LVCMOS 2.5 V information: LVCMOS 2.5/5.0 V Table 2-75 on page 2-154 Table 2-76 on page ...
Page 173
... HSTL Class II 1.50 V SSTL3 Class I 3.30 V SSTL3 Class II 3.30 V SSTL2 Class I 2.50 V SSTL2 Class II 2.50 V LVDS, BLVDS, M- 2.50 V LVDS LVPECL 3.30 V Actel Fusion Family of Mixed Signal FPGAs Input Reference Voltage ) (V ) CCI_TYP REF_TYP – – – – – – – 1.00 V 1.00 V 0.80 V ...
Page 174
... LVCMOS 1.5 V PCI (3.3 V) ✓ PCI-X (3.3 V) LVDS, BLVDS, M-LVDS LVPECL Note: *This feature does not apply to the standard I/O banks, which are the north I/O banks of AFS090 and AFS250 devices Table 2-81 and SKEW OUT_DRIVE (all macros (output only) ...
Page 175
... Actel Fusion Family of Mixed Signal FPGAs ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ...
Page 176
... MUX at CCC location m. Standard I/O Bank CCC Bank 0 "A" Bank 3 AFS090 CCC/PLL "F" AFS250 Bank 3 CCC Bank 2 (analog) "E" Analog Quads R e visio n 1 Figure 2-112 on page 2-161). The name CCC "B" ...
Page 177
... CCC Bank 0 "A" Bank 4 CCC/PLL "F" Bank 4 CCC "E" Figure 2-112 • Naming Conventions of Fusion Devices with Four I/O Banks Actel Fusion Family of Mixed Signal FPGAs Pro I/O Bank CCC Bank 1 "B" Bank 2 AFS600 CCC/PLL AFS1500 "C" Bank 2 CCC Bank 3 (analog) " ...
Page 178
Device Architecture User I/O Characteristics Timing Model I/O Module (Registered 1. LVPECL D (Pro IO Banks 0.24 ns ICLKQ t = 0.26 ns Input LVTTL/LVCMOS ISUD 3.3 V (Pro IO banks 0.90 ...
Page 179
... VIH V trip PAD 50% Y GND t PY (R) t PYS (R) 50% DIN t GND DOUT (R) Figure 2-114 • Input Buffer Timing Model and Delays (example) Actel Fusion Family of Mixed Signal FPGAs t DIN CLK I/O interface (R), t (F)) PY (R), t (F)) PYS PYS (R), t (F)) DIN DIN V trip ...
Page 180
Device Architecture D From Array Figure 2-115 • Output Buffer Model and Delays (example DOUT D Q DOUT CLK t = MAX(t DP I/O Interface t DOUT t t DOUT DOUT (R) VCC (F) 50% 50% ...
Page 181
... EOUT t ZL PAD V trip VOL D 50% 50 EOUT (R) VCC 50% EOUT t ZLS PAD V trip VOL Figure 2-116 • Tristate Output Buffer Timing Model and Delays (example) Actel Fusion Family of Mixed Signal FPGAs ZLS ZHS EOUT PAD t = MAX(t (R). t (F)) EOUT EOUT EOUT VCC VCC ...
Page 182
Device Architecture Overview of I/O Performance Summary of I/O DC Input and Output Levels – Default I/O Software Settings Table 2-83 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions Applicable to ...
Page 183
... V V 0.8 2 3.6 0.7 1.7 3.6 0.35 * VCCI 0.65 * VCCI 3.6 0.35 * VCCI 0.65 * VCCI 3.6 1 Commercial µA µ Actel Fusion Family of Mixed Signal FPGAs VOL VOH Max. Min 0.4 2 0.7 1 0.45 VCCI – 0. 0.25 * VCCI 0.75 * VCCI Industrial µA µ ...
Page 184
Device Architecture Summary of I/O Timing Characteristics – Default I/O Software Settings Table 2-87 • Summary of AC Measuring Points Applicable to All I/O Bank Types Input Reference Voltage Standard 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS ...
Page 185
... Table 3-6 on page 3 Actel Fusion Family of Mixed Signal FPGAs – – – – – – ns – – – ...
Page 186
Device Architecture Table 2-90 • Summary of I/O Timing Characteristics – Software Default Settings Commercial Temperature Range Conditions: T Worst-Case VCCI = I/O Standard Dependent Applicable to Advanced I/Os I/O Standard 3.3 V LVTTL High 35 pF 3.3 ...
Page 187
... These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend , drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website: http://www.actel.com/techdocs/models/ibis.html VOLspec / I ...
Page 188
... These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend , drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website: http://www.actel.com/techdocs/models/ibis.html VOLspec / I (PULL-DOWN-MAX) 3 ...
Page 189
... These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend , drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website: http://www.actel.com/techdocs/models/ibis.html VOLspec / I ...
Page 190
Device Architecture Table 2-95 • I/O Short Currents I OSH Applicable to Pro I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS Applicable to Advanced I/O Banks 3.3 V LVTTL / ...
Page 191
... The I/O design does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. OSL (continued) Drive Strength I OSH 169 Per PCI/PCI-X 103 specification events depends on the junction temperature. The OSH OSL Actel Fusion Family of Mixed Signal FPGAs (mA)* I (mA)* OSL 124 109 175 ...
Page 192
... Schmitt trigger is disabled, can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board noise. Actel recommends signal integrity evaluation/characterization of the system to ensure there is no excessive noise coupling into input signals ...
Page 193
... Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. Test Point Data Path 35 pF Figure 2-117 • AC Loading Actel Fusion Family of Mixed Signal FPGAs VIH VOL VOH I OL Max. ...
Page 194
Device Architecture Table 2-100 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) 0 Note: *Measuring point = V . See trip Timing Characteristics Table 2-101 • 3.3 V LVTTL / 3.3 V LVCMOS Low ...
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... Std. 0.66 3.21 0.04 –1 0.56 2.73 0.04 –2 0.49 2.39 0.03 Note: For the derating values at specific junction temperature and voltage supply levels, refer to page 3-9. Actel Fusion Family of Mixed Signal FPGAs = 70°C, Worst-Case VCC = 1.425 EOU PYS 1.20 1.57 ...
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Device Architecture Table 2-103 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial Temperature Range Conditions: T Worst-Case VCCI = 3.0 V Applicable to Advanced I/Os Drive Speed Strength Grade t t DOUT Std. 0.66 ...
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... Actel Fusion Family of Mixed Signal FPGAs Units LZ HZ ZLS ZHS 2.65 2.61 10.03 8.82 ns 2.25 2.22 8.54 7.51 ns 1.98 1.95 7.49 6 ...
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Device Architecture Table 2-106 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial Temperature Range Conditions: T Worst-Case VCCI = 3.0 V Applicable to Standard I/Os Drive Speed Strength Grade t DOUT 2 mA Std. 0.66 –1 0.56 ...
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... R to VCCI for GND for t Test Point Enable Path 35 pF for for t HZ Measuring Point* (V) 1.2 for a complete table of trip points Actel Fusion Family of Mixed Signal FPGAs OSL OSH IL IH Max. Max µA µ ...
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Device Architecture Timing Characteristics Table 2-109 • 2.5 V LVCMOS Low Slew Commercial Temperature Range Conditions: T Worst-Case VCCI = 2.3 V Applicable to Pro I/Os Drive Speed Strength Grade t t DOUT Std. 0.60 12.00 0.04 ...