AFS250-FGG256 Actel, AFS250-FGG256 Datasheet - Page 151

• Manufacturer Part Number: AFS250-FGG256
• Description: FPGA - Field Programmable Gate Array 250K System Gates
• Manufacturer: Actel

Specifications of AFS250-FGG256

• Processor Series: AFS250
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 114
• Data Ram Size: 36864
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 250 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 2-97 • Fusion Pro I/O Bank Detail Showing VREF Minibanks (north side ofAFS600 and AFS1500)
Table 2-64 • I/O Standards Supported by Bank Type
I/O Bank
Standard I/O
Advanced I/O LVTTL/LVCMOS 3.3 V,
Pro I/O
LVTTL/LVCMOS 3.3 V,
LVCMOS 2.5 V / 1.8 V / 1.5 V,
LVCMOS 2.5/5.0 V
LVCMOS 2.5 V / 1.8 V / 1.5 V,
LVCMOS 2.5/5.0 V, 3.3 V PCI /
3.3 V PCI-X
LVTTL/LVCMOS 3.3 V,
LVCMOS 2.5 V / 1.8 V / 1.5 V,
LVCMOS 2.5/5.0 V, 3.3 V PCI /
3.3 V PCI-X
Single-Ended I/O Standards
between 8 and 18 I/Os.
VREF signal scope is
CCC
I/O Pad
–
LVPECL
LVDS
LVPECL
LVDS
minibanks within
Up to five VREF
Differential I/O
an I/O bank
Standards
R e v i s i o n 1
CCC
If needed, the VREF for a given
minibank can be provided by
any I/O within the minibank.
and
and
–
–
GTL+ 2.5 V / 3.3 V, GTL
2.5 V / 3.3 V, HSTL Class I and II,
SSTL2 Class I and II, SSTL3 Class I
and II
in VREF minibanks
Actel Fusion Family of Mixed Signal FPGAs
signal for all I/Os
Common VREF
Voltage-Referenced
CCC
Swap
Hot-
Yes
Yes
2- 135
–