AFS250-FGG256 Actel, AFS250-FGG256 Datasheet - Page 42
AFS250-FGG256
Manufacturer Part Number
AFS250-FGG256
Description
FPGA - Field Programmable Gate Array 250K System Gates
Manufacturer
Actel
Datasheet
1.AFS600-PQG208.pdf
(330 pages)
Specifications of AFS250-FGG256
Processor Series
AFS250
Core
IP Core
Maximum Operating Frequency
1098.9 MHz
Number Of Programmable I/os
114
Data Ram Size
36864
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
250 K
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Price
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Manufacturer:
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ACTEL
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Part Number:
AFS250-FGG256I
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Device Architecture
2- 26
Global Buffers with Programmable Delay
The CLKDLY macro is a pass-through clock source that does not use the PLL, but provides the ability to
delay the clock input using a programmable delay
clock input and adds a user-defined delay element. This macro generates an output clock phase shift
from the input clock.
The CLKDLY macro can be driven by an INBUF macro to create a composite macro, where the I/O
macro drives the global buffer (with programmable delay) using a hardwired connection. In this case, the
I/O must be placed in one of the dedicated global I/O locations.
Many specific INBUF macros support the wide variety of single-ended and differential I/O standards
supported by the Fusion family. The available INBUF macros are described in the
ProASIC3/E Macro Library Guide.
The CLKDLY macro can be driven directly from the FPGA core.
The CLKDLY macro can also be driven from an I/O that is routed through the FPGA regular routing
fabric. In this case, users must instantiate a special macro, PLLINT, to differentiate from the hardwired
I/O connection described earlier.
The visual CLKDLY configuration in the SmartGen part of the Libero IDE and Designer tools allows the
user to select the desired amount of delay and configures the delay elements appropriately. SmartGen
also allows the user to select the input clock source. SmartGen will automatically instantiate the special
macro, PLLINT, when needed.
Figure 2-21 • Fusion CCC Options: Global Buffers with Programmable Delay
PADN
PADP
Input LVDS/LVPECL Macro
PAD
Clock Source
INBUF* Macro
Y
Y
R e visio n 1
CLK
DLYGL[4:0]
(Figure
Clock Conditioning
2-21). The CLKDLY macro takes the selected
GL
Fusion, IGLOO/e and
Output
GLA
or
GLB
or
GLC
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