AFS250-FGG256 Actel, AFS250-FGG256 Datasheet - Page 60

• Manufacturer Part Number: AFS250-FGG256
• Description: FPGA - Field Programmable Gate Array 250K System Gates
• Manufacturer: Actel

Specifications of AFS250-FGG256

• Processor Series: AFS250
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 114
• Data Ram Size: 36864
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 250 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Architecture
Figure 2-33 • Flash Memory Block Diagram
2- 44
OVERWRITEPROTECT
PAGELOSSPROTECT
UNPROTECTPAGE
OVERWRITEPAGE
DATAWIDTH[1:0]
LOCKREQUEST
DISCARDPAGE
PAGESTATUS
ERASEPAGE
SPAREPAGE
ADDDR[17:0]
STATUS[1:0]
READNEXT
AUXBLOCK
PROGRAM
WD[31 :0]
RD[31:0]
RESET
BUSY
Flash Memory Block Diagram
A simplified diagram of the flash memory block is shown in
The logic consists of the following sub-blocks:
The FB stores error correction information with each block to perform single-bit error correction and
double-bit error detection on all data blocks.
WEN
PIPE
REN
CLK
•
•
•
•
Flash Array
Contains all stored data. The flash array contains 64 sectors, and each sector contains 33 pages
of data.
Page Buffer
A page-wide volatile register. A page contains 8 blocks of data and an AUX block.
Block Buffer
Contains the contents of the last block accessed. A block contains 128 data bits.
ECC Logic
Output
MUX
Control
Logic
Block Buffer
(128 bits)
R e visio n 1
ECC
Logic
Figure
Page Buffer = 8 Blocks
Plus AUX Block
2-33.
Flash Array = 64 Sectors