AFS250-FGG256 Actel, AFS250-FGG256 Datasheet - Page 110

• Manufacturer Part Number: AFS250-FGG256
• Description: FPGA - Field Programmable Gate Array 250K System Gates
• Manufacturer: Actel

Specifications of AFS250-FGG256

• Processor Series: AFS250
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 114
• Data Ram Size: 36864
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 250 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Architecture
Figure 2-75 • Gate Driver
2- 94
Off-Chip
On-Chip
Pads
Power
Gate Driver
The Fusion Analog Quad includes a Gate Driver connected to the Quad's AG pin
Designed to work with external p- or n-channel MOSFETs, the Gate driver is a configurable current sink
or source and requires an external pull-up or pull-down resistor. The AG supports 4 selectable gate drive
levels: 1 µA, 3 µA, 10 µA, and 30 µA
Drive mode in which it can sink 20 mA; in this mode the switching rate is approximately 1.3 MHz with
100 ns turn-on time and 600 ns turn-off time. Modeled on an open-drain-style output, it does not output a
voltage level without an appropriate pull-up or pull-down resistor. If 1 V is forced on the drain, the current
sinking/sourcing will exceed the ability of the transistor, and the device could be damaged.
The AG pad is turned on via the corresponding GDONx pin in the Analog Block macro, where x is the
number of the corresponding Analog Quad for the AG pad to be enabled (GDON0 to GDON9).
The gate-to-source voltage (V
times the external pull-up or pull-down resistor value
The rate at which the gate voltage of the external MOSFET slews is determined by the current, I
sourced or sunk by the AG pin and the gate-to-source capacitance, C
approximation, the slew rate is given by
AV
Prescaler
Digital
Input
Monitor Block
Voltage
(DAVOUTx)
Line Side
To FPGA
To Analog MUX
Monitor / Instr
AC
Prescaler
Amplifier
Digital
Current
Input
gs
) of the external MOSFET is limited to the programmable drive current
Monitor Block
(DACOUTx)
Current
To FPGA
V
Analog Quad
(Figure 2-76 on page
gs
EQ
≤ I
To Analog MUX
g
6.
dv/dt = I
R e visio n 1
R
× (R
pullup
pullup
g
Gate Driver
(EQ
From FPGA
MOSFET
/ C
(GDONx)
Power
or R
GS
5).
AG
pulldown
2-95). The AG also supports a High Current
Driver
Gate
)
GS
, of the external MOSFET. As an
AT
Temperature
Digital
Input
Prescaler
Monitor
Monitor Block
Load Side
Temperature
(DATOUTx)
To FPGA
To Analog MUX
(Figure
2-75).
EQ 5
EQ 6
g
,