AFS250-FGG256 Actel, AFS250-FGG256 Datasheet - Page 235

• Manufacturer Part Number: AFS250-FGG256
• Description: FPGA - Field Programmable Gate Array 250K System Gates
• Manufacturer: Actel

Specifications of AFS250-FGG256

• Processor Series: AFS250
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 114
• Data Ram Size: 36864
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 250 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 2-138 • Output Register Timing Diagram
Table 2-174 • Output Data Register Propagation Delays
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
OCLKQ
OSUD
OHD
OSUE
OHE
OCLR2Q
OPRE2Q
OREMCLR
ORECCLR
OREMPRE
ORECPRE
OWCLR
OWPRE
OCKMPWH
OCKMPWL
Enable
Preset
Clear
DOUT
CLK
Data_out
For the derating values at specific junction temperature and voltage supply levels, refer to
page
Commercial Temperature Range Conditions: T
Output Register
3-9.
Clock-to-Q of the Output Data Register
Data Setup Time for the Output Data Register
Data Hold Time for the Output Data Register
Enable Setup Time for the Output Data Register
Enable Hold Time for the Output Data Register
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Asynchronous Clear Minimum Pulse Width for the Output Data Register
Asynchronous Preset Minimum Pulse Width for the Output Data
Register
Clock Minimum Pulse Width High for the Output Data Register
Clock Minimum Pulse Width Low for the Output Data Register
Timing Characteristics
50%
50%
t
1
OSUE
t
OHE
50%
50%
t
OSUD
Description
0
t
t
OHD
OCLKQ
50%
50%
50%
t
OWPRE
t
OPRE2Q
50%
50%
R e v i s i o n 1
t
t
ORECPRE
50%
OCLR2Q
50%
J
= 70°C, Worst-Case VCC = 1.425 V
t
OWCLR
50%
50%
50%
t
ORECCLR
Actel Fusion Family of Mixed Signal FPGAs
50%
0.59
0.31
0.00
0.44
0.00
0.80
0.80
0.00
0.22
0.00
0.22
0.22
0.22
0.36
0.32
–2
t
OCKMPWH
t
50%
OREMPRE
0.67
0.36
0.00
0.50
0.00
0.91
0.91
0.00
0.25
0.00
0.25
0.25
0.25
0.41
0.37
–1
50%
t
OCKMPWL
Table 3-7 on
Std.
0.79
0.42
0.00
0.59
0.00
1.07
1.07
0.00
0.30
0.00
0.30
0.30
0.30
0.48
0.43
t
OREMCLR
50%
50%
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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