AFS250-FGG256 Actel, AFS250-FGG256 Datasheet - Page 159
AFS250-FGG256
Manufacturer Part Number
AFS250-FGG256
Description
FPGA - Field Programmable Gate Array 250K System Gates
Manufacturer
Actel
Datasheet
1.AFS600-PQG208.pdf
(330 pages)
Specifications of AFS250-FGG256
Processor Series
AFS250
Core
IP Core
Maximum Operating Frequency
1098.9 MHz
Number Of Programmable I/os
114
Data Ram Size
36864
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
250 K
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Table 2-71 • Levels of Hot-Swap Support
Hot
Swapping
Level
1
2
3
4
Hot-swap on
Description
while reset
Cold-swap
Hot-swap
Hot-swap
Hot-Swap Support
Hot-swapping (also called hot plugging) is the operation of hot insertion or hot removal of a card in (or
from) a powered-up system. The levels of hot-swap support and examples of related applications are
described in
compliance is required.
while bus
an active
bus
idle
to Device Bus State
Applied
Power
Table
Yes
Yes
Yes
No
2-71. The I/Os also need to be configured in hot insertion mode if hot plugging
–
Held in
reset state
Held idle
(no ongoing
I/O
processes
during
insertion/re
moval)
Bus may
have active
I/O
processes
ongoing,
but device
being
inserted or
removed
must be
idle.
–
Must be made
and
maintained for
1 ms before,
during, and
after insertion/
removal
Same as
Level 2
Same as
Level 2
Connection
Ground
Card
R e v i s i o n 1
to Bus Pins
–
–
Must remain
glitch-free
during
power-up or
power-down
Same as
Level 3
Connected
Circuitry
Device
System and card with
Actel FPGA chip are
powered down, then
card gets plugged into
system, then power
supplies are turned on
for system but not for
FPGA on card.
In PCI hot plug
specification, reset
control circuitry
isolates the card
busses until the card
supplies are at their
nominal operating
levels and stable.
Board bus shared
with card bus is
"frozen," and there is
no toggling activity on
bus. It is critical that
the logic states set on
the bus signal do not
get disturbed during
card
insertion/removal.
There is activity on
the system bus, and it
is critical that the logic
states set on the bus
signal do not get
disturbed during card
insertion/removal.
Cards that Contain
Actel Fusion Family of Mixed Signal FPGAs
Application with
Fusion Devices
Example of
Compliant I/Os
can but do not
have to be set to
hot insertion
mode.
Compliant I/Os
can but do not
have to be set to
hot insertion
mode.
Compliant with
cards with two
levels of staging.
I/Os have to be
set to hot
insertion mode.
Compliant with
cards with two
levels of staging.
I/Os have to be
set to hot
insertion mode.
Fusion Devices
Compliance of
2- 143
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