AFS250-FGG256 Actel, AFS250-FGG256 Datasheet - Page 218

FPGA - Field Programmable Gate Array 250K System Gates

AFS250-FGG256

Manufacturer Part Number
AFS250-FGG256
Description
FPGA - Field Programmable Gate Array 250K System Gates
Manufacturer
Actel
Datasheet

Specifications of AFS250-FGG256

Processor Series
AFS250
Core
IP Core
Maximum Operating Frequency
1098.9 MHz
Number Of Programmable I/os
114
Data Ram Size
36864
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
250 K
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Manufacturer:
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Device Architecture
Table 2-138 • Minimum and Maximum DC Input and Output Levels
Figure 2-123 • AC Loading
Table 2-139 • AC Waveforms, Measuring Points, and Capacitive Loads
Table 2-140 • 2.5 V GTL
2- 20 2
2.5 GTL
Drive
Strength
25 mA
Notes:
1. I
2. I
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
Input Low (V)
VREF – 0.05
Note:
Speed
Grade
Note:
Std.
–1
–2
larger when operating outside recommended ranges.
IL
IH
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
3
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
*Measuring point = V
For the derating values at specific junction temperature and voltage supply levels, refer to
page
t
Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V, VREF = 0.8 V
0.66
0.56
0.49
DOUT
Min.
–0.3
2.5 V GTL
Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier
input buffer and an open-drain output buffer. The V
3-9.
V
Timing Characteristics
Input High (V)
VREF – 0.05 VREF + 0.05
VIL
VREF + 0.05
2.13
1.81
1.59
t
DP
Max.
V
trip
. See
0.04
0.04
0.03
t
DIN
Table 2-87 on page 2-168
Min.
V
2.46
2.09
1.83
Measuring Point* (V)
t
PY
VIH
Test Point
t
EOUT
0.43
0.36
0.32
0.8
Max.
3.6
V
GTL
R e visio n 1
2.16
1.84
1.61
t
ZL
Max.
VOL
VTT
0.4
V
for a complete table of trip points.
CCI
25
10 pF
pin should be connected to 2.5 V.
2.13
1.81
1.59
VREF (typ.) (V)
t
ZH
VOH
Min.
V
0.8
t
mA
I
LZ
25
OL
mA
I
25
OH
t
VTT (typ.) (V)
HZ
Max.
mA
I
124
OSL
1.2
4.40
3.74
3.28
t
3
ZLS
Max.
I
mA
169
OSH
3
t
4.36
3.71
3.26
ZHS
Table 3-7 on
C
LOAD
µA
I
10
IL
1
10
4
Units
(pF)
ns
ns
ns
µA
I
10
IH
2
4

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